I am trying to create multiple adders via Verilog to compare the speed of each adder.
I am getting the following error Unable to bind parameter WIDTH in arith_unit
This is my code so far:
module arith_unit
#(
parameter ADDER_TYPE = 0,
parameter WIDTH = 8)
(input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum,
);
////////////////////////////////////////////////////////////////
if (ADDER_TYPE == 0)
begin
ripple_carry rc1 (a, b, cin, sum, cout);
end
////////////////////////////////////////////////////////////////
else if (ADDER_TYPE == 1)
begin
carry_bypass cb1 (a, b, cin, sum, cout);
end
//// more else statment for ADDER_TYPE...
endmodule
//////////////////////////////////////////////////////////////////
module ripple_carry_4_bit(a, b, cin, sum, cout);
input [3:0] a,b;
input cin;
wire c1,c2,c3;
output [3:0] sum;
output cout;
full_adder fa0(.a(a[0]), .b(b[0]),.cin(cin), .sum(sum[0]),.cout(c1));
full_adder fa1(.a(a[1]), .b(b[1]), .cin(c1), .sum(sum[1]),.cout(c2));
full_adder fa2(.a(a[2]), .b(b[2]), .cin(c2), .sum(sum[2]),.cout(c3));
full_adder fa3(.a(a[3]), .b(b[3]), .cin(c3), .sum(sum[3]),.cout(cout));
endmodule
////////////////////////////////////////////////////////////////
module ripple_carry (a, b, cin, sum, cout);
input [WIDTH-1:0] a,b;
input cin;
wire c1,c2,c3, c4, c5, c6, c7;
output [WIDTH-1:0] sum;
output cout;
if (WIDTH == 8) begin //<-------- compiler is pointing here as the problem
ripple_carry_4_bit rca1 (.a(a[3:0]),.b(b[3:0]),.cin(cin), .sum(sum[3:0]),.cout(c1));
ripple_carry_4_bit rca2 (.a(a[7:4]),.b(b[7:4]),.cin(c1), .sum(sum[7:4]),.cout(cout));
end
else if (WIDTH == 16) begin
ripple_carry_4_bit rca1 (.a(a[3:0]),.b(b[3:0]),.cin(cin), .sum(sum[3:0]),.cout(c1));
ripple_carry_4_bit rca2 (.a(a[7:4]),.b(b[7:4]),.cin(c1), .sum(sum[7:4]),.cout(c2));
ripple_carry_4_bit rca3 (.a(a[11:8]),.b(b[11:8]),.cin(c2), .sum(sum[11:8]),.cout(c3));
ripple_carry_4_bit rca4 (.a(a[15:12]),.b(b[15:12]),.cin(c3), .sum(sum[15:12]),.cout(cout));
end
//// more else statment for 32 & 64 bits...
endmodule
I looked online and it seems that my if and else statements are correct. So I am assuming that my WIDTH is declared wrong? I tried passing in WIDTH via module ripple_carry (a, b, cin, sum, cout, WIDTH); kind of how you would do it with C++, but I still get the same error.
I've tested the ripple_carry on its own (no if statements, no parameter) with 8 bits, 16 bits, etc. and it works fine. So I know that my logic for the ripple_carry is fine.
Please help me, thank you.
It would have helped to show the exact error message with the line number, but you are missing a WIDTH parameter declaration in the module ripple_carry.
module ripple_carry #(parameter WIDTH=8)(...
And add it when instantiating it inside the generate block.
ripple_carry #(WIDTH) (a, b, cin, sum, cout);
Related
So I am trying to do an assignment for my class but for some reason I cant get the output to match with what I need. I have to make a program that asks for 6 integers and display the smallest even and odd. There will be 3 even entered and 3 odd but the order is unknown and we can't use loops or arrays. This sample is just what i have so far but I can't seem to understand why a and b won't work.
int a, b, c, d, e, f, smallEven=0, smallOdd=0;
cout<<"Enter a number:\n";
cin>>a;
if (a%2==0)
smallEven=a;
else if (a%2==1)
smallOdd=a;
cout<<"Enter a number:\n";
cin>>b;
if (b%2==0)
if (smallEven=0)
smallEven=b;
else if (b<smallEven)
smallEven=b;
else if (b%2==1)
if (smallOdd=0)
smallOdd=b;
else if (b<smallOdd)
smallOdd=b;
cout<<smallEven;
cout<<smallOdd;
The reason why this isn't doing what you're expecting is that you're using an assignment operator (=) instead of the comparison operator for equality (==) in two places:
if (b%2==0)
if (smallEven=0) // should be == here
smallEven=b;
else if (b<smallEven)
smallEven=b;
else if (b%2==1)
if (smallOdd=0) // should be == here
smallOdd=b;
else if (b<smallOdd)
smallOdd=b;
So I am trying to design a 4-bit carry select adder in verilog, and am using the following code for the design:
module fullAdder (S,Cout,P,G,A,B,Cin);
// Define all inputs and outputs for single bit Fulll Adder
output S;
output Cout;
output P;
output G;
input A;
input B;
input Cin;
// Full Adder body, define structure and internal wiring
wire t1, t2, t3;
xor xor1 (t1, A, B);
xor xor2 (S, t1, Cin);
or or1 (P, A, B);
and and1 (G, A, B);
and and2 (t2, P, Cin);
or or2 (Cout, t2, G);
endmodule
module carrySelect (sum, cout, a, b, cin);
output [3:0] sum; //sum output of the adder, 4 bits wide
output cout; //carry out of the adder
input [3:0] a; //input a, 4 bits wide
input [3:0] b; //input b, 4 bits wide
input cin; //carry in of the adder
reg ch, cl; //temporary variables to define cases that previous carry is high or low
wire [3:0] C; //carry bus
wire [3:0] P,G; //buses for P and G outputs of fullAdder
wire [1:0] s0, s1, s2, s3; //temporary buses for cases of sums
wire [1:0] c0, c1, c2, c3; //temporary buses for cases of carries
assign ch = 1; //assign ch to high and cl to low
assign cl = 0;
//least significant full adder computation
fullAdder f0_h (s0[0],c0[0],p0[0], g0[0], a[0], b[0], ch);
fullAdder f0_l (s0[1],c0[1],p0[1], g0[1], a[0], b[0], cl);
fullAdder f1_h (s1[0],c1[0],p1[0], g1[0], a[0], b[0], ch);
fullAdder f1_l(s1[1],c1[1],p1[1], g1[1], a[0], b[0], cl);
fullAdder f2_h (s2[0],c2[0],p2[0], g2[0], a[0], b[0], ch);
fullAdder f2_l (s2[1],c2[1],p2[1], g2[1], a[0], b[0], cl);
//most significant full adder computation
fullAdder f3_h (s3[0],c3[0],p3[0], g3[0], a[0], b[0], ch);
fullAdder f3_l (s3[1],c3[1],p3[1], g3[1], a[0], b[0], cl);
//select output depending on values of carries
if (cin == 1) begin
assign sum[0] = s0[0];
assign C[0] = c0[0];
end else begin
assign sum[0] = s0[1];
assign C[0] = c0[1];
end
if(C[0] == 1) begin
assign sum[1] = s1[0];
assign C[1] = c1[0];
end else begin
assign sum[1] = s1[1];
assign C[1] = c1[1];
end
if(C[1]) begin
assign sum[2] = s2[0];
assign C[2] = c2[0];
end else begin
assign sum[2] = s2[1];
assign C[2] = c2[1];
end
if(C[2]) begin
assign sum[3] = s3[0];
assign C[3] = c3[0];
end else begin
assign sum[3] = s3[1];
assign C[3] = c3[1];
end
//assign carry out
assign cout = C[3];
endmodule
where the full adder is completely functional, so there are no problems there. I get errors from the if statements when I try to compile the code, and get the warning about implicit definitions and error of not being able to evaluate genvar of the conditional in the ifs. I am fairly new to verilog, so I apologize if this is a trivial fix. Any help is appreciated.
EDIT1:Error/warning message thrown
design.sv:57: warning: implicit definition of wire fullAdderTest.UUT.cin.
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:65: warning: implicit definition of wire fullAdderTest.UUT.C.
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
4 error(s) during elaboration.
An if statement outside of an always or initial block is treated as a if it was inside an generate block. A generate's if statement will accepts literal constants (hard coded values), parameters, and genvars. It will not accept net or register types (i.e: wire, reg, integer, etc). Generate blocks are evaluated during elaboration and therefore cannot depend on simulation variables with dynamic values.
You want conditionally select the values for sum and C based on input values. There are a few options to do this:
One option is to make an inline condition statement:
assign sum[0] = cin ? s0[0] : s0[1];
assign C[0] = cin ? c0[0] : c0[1];
// ...
Or you can select the index (same effect):
assign sum[0] = s0[!cin];
assign C[0] = c0[!cin];
assign sum[1] = s1[!C[0]];
assign C[1] = c1[!C[0]];
// ...
Or make sum and C reg types and put all the if statements inside an always block (remove the assigns):
always #* begin
if (cin == 1) begin
sum[0] = s0[0];
C[0] = c0[0];
end
else begin
sum[0] = s0[1];
C[0] = c0[1];
end
// ...
end
i'm not that much in verilog
i'm trying to call a module inside if statement
i can't find the answer in google or may i didn't understand what should i do with MY CODE
my code is a full adder addition
i need the IF cause i want to add other things
this is my code:
module top (a,b,cin,Cout,Ctemp,sum,clk,X);
input [3:0] a,b;
input X;
input cin,clk;
output reg[3:0] sum;
output reg[2:0] Ctemp;
output reg Cout;
always#(posedge clk)
begin
generate
if (X==1)
add bit0(a[0], b[0], cin, sum[0], Ctemp[0]); //here i need to call add module
add bit1(a[1], b[1], Ctemp[0], sum[1], Ctemp[1]);
add bit2(a[2], b[2], Ctemp[1], sum[2], Ctemp[2]);
add bit3(a[3], b[3], Ctemp[2], sum[3], Cout);
end
endgenerate
endmodule
module add(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum = (~a*~b*cin)+(~a*b*~cin)+(a*~b*~cin)+(a*b*cin);
assign cout = (a*b)+(a*cin)+(b*cin);
endmodule
I'll give some hints. you need to move the module instantiations outside the always block (above or below). Then add additional wire declarations for for the outputs of the module that you will be flopping. I recommend modifying your module instantiation port connections to explicit (connect-by-name) instead of implicit (connect-by-order). This way even of the port order changes, the connectivity will be maintained. Extremely useful for modules with a lot of ports.
The body of your top module should looks something like this:
// ...
add bit3( .a(a[3]), .b(b[3]), .cin(Ctemp[2]), .sum(pre_sum[3]), .cout(pre_cout));
always#(posedge clk)
begin
if (X==1) begin
sum <= pre_sum;
Cout <= pre_cout;
end
end
Other recommendation: Use ANSI style module header; it is less typing and easier to maintain. Non-ANSI style was required for really old simulations before this century. Example:
module top (
input [3:0] a, b,
input cin,
output reg Cout,
output [2:0] Ctemp,
output reg [3:0] sum,
input clk,
input X );
I need help with this problem POUR1. I think
it can be solved with bruteforce approach, but I read that it is a graph problem (BFS). I solved problems like ABCPATH, LABYR1, PT07Y, PT07Z, BITMAP, ...
But I don't know how to approach POUR1 in BFS manner.
Can someone give me some advice?
Problem statement:
Given two vessels, one of which can accommodate a litres of water and the other - b litres of water, determine the number of steps required to obtain exactly c litres of water in one of the vessels.
At the beginning both vessels are empty. The following operations are counted as 'steps':
emptying a vessel,
filling a vessel,
pouring water from one vessel to the other, without spilling, until one of the vessels is either full or empty.
Input:
An integer t, 1<=t<=100, denoting the number of testcases, followed by t sets of input data, each consisting of three positive integers a, b, c, not larger than 40000, given in separate lines.
Output:
For each set of input data, output the minimum number of steps required to obtain c litres, or -1 if this is impossible.
Example:
Sample input:
2
5
2
3
2
3
4
Sample output:
2
-1
This question has a simpler solution. No need for BFS. Ad-hoc would do good.
method 1 - fill A, empty it into B. whenever A becomes empty fill it back, whenever B becomes full empty it. (all the above-mentioned actions count as individual moves). Continue this process until you arrive at the required amount of water in any one of the vessels. Get the number of moves here. (say C1).
method 2 - fill B, empty it into A. whenever B becomes empty fill it back, whenever A becomes full empty it. Continue this until you arrive at the required amount. Get the number of moves say C2).
The answer is min(C1,C2).
Source code in C++:
#include < cstdio >
#include < algorithm >
using namespace std;
int pour(int A, int B, int C) {
int move = 1, a = A, b = 0, tfr;
while (a != C && b != C) {
tfr = min(a, B - b);
b += tfr;
a -= tfr;
move++;
if (a == C || b == C)
break;
if (a == 0) {
a = A;
move++;
}
if (b == B) {
b = 0;
move++;
}
}
return move;
}
/** Reason for calculating GCD of a,b is to check whether an integral solution of
* equation of form ax + by = c exist or not, to dig deeper read Diophantine Equations
*/
int gcd(int a, int b) {
if (b == 0)
return a;
return gcd(b, a % b);
}
int main() {
int t, a, b, c;
scanf("%d", & t);
while (t--) {
scanf("%d%d%d", & a, & b, & c);
if (c > a && c > b)
printf("-1\n");
else if (c % gcd(a, b) != 0)
printf("-1\n");
else if (c == a || c == b)
printf("1\n");
else
printf("%d\n", min(pour(a, b, c), pour(b, a, c)));
}
return 0;
}
Consider the set of all a priori possibles states (eg [3, 7] meaning Vessel1 contains 3 litters and vessel2 contains 7 litters). You have a directed graph whose vertices are those states and whose edges are the possible moves. The question is to find a path in the graph joining the state [0, 0] to either a state of type [c, ?] or a state of type [?, c]. Such a path is typically searched by a BFS.
I am new to FORTRAN, and must write a FORTRAN 77 program to read the following format from a file redirection or standard input:
[CHARACTER] [REAL] [REAL] [REAL] ... (can have any number of these)
D [INTEGER] (only one of these)
[REAL] [REAL] [REAL] ... (can have any number of these)
example input could be:
T 1.0 2.0 3.0
S 1.0 2.0 4.0
Y 3.0 4.0 5.0
D 2
3.0 5.0 6.0
4.5 4.6 5.6
My native language is C++, so I'm new to this whole idea of a read statement going to the next line automatically.
So far, I have the following code:
c234567
character*1 D
character*1 LETTER
real X, Y, Z
integer lines
real point1, point2, point3
85 format (3F10.6)
100 format (A1, 5X, F10.6, 5X, F10.6, 4X, F10.6)
990 format (A, I10)
MAX = 6
LETTER = 'Z'
D = 'D'
read *, LETTER, X, Y, Z
10 if(LETTER .ne. D) then
write (6, 100) LETTER, X, Y, Z
read *, LETTER, X, Y, Z
goto 10
else
goto 20
endif
C =====================================================
20 lines = aint(X)
write (*,990) 'LINES: ', lines
write (6, 85) X, Y, Z
read *, Z
write (6, 85) X, Y, Z
end
As you can see, I get the first portion of the input fine, but after that it kind of all goes to mush because of the read statement: read*, Z going to the next line. In my specific input file provided above, I get the 2 after the D, and the next two values (3.0, 5.0) but I skip the 6.0
Any help would be great. Thanks.
If you know that your lines will never exceed a maximum length, I suggest to read the whole line and then to parse the line according to your rules.
An example using a maximum line length of 1024 characters:
CHARACTER*1024 line
CHARACTER letter
100 FORMAT (A)
READ(*,100) line
READ(line, *) letter
IF (letter .eq. 'T') THEN
...
END IF
Maybe this technique works for you.
I haven't even looked at you code but I would suggest a strategy like this
(1) read the initial character of the line
if not "D" then
read reals
store the line
loop to (1)
else
read one integer
store the line
break
endif
read lines of reals until end-of-file
My fortran is very rusty, but I believe that there are constructs that will help you with this. Certainly the END modifier to READ is going to be helpful with the last bit.
After a little experimenting, I find that gfortran seems to support the old trailing $ for non-advancing input convention and advance='no'. However, g77 does not. I can't speak to any other compiler--as far as I know this was never standardized until fortran 90 where advance='no' was introduced.
Demo code that works in gfortran, but not in g77
program temp
c234567
character a
integer i
real x, y, z, w(50)
c This or with (*,'(A1 $)')
read (*,'(A1)',advance='no') a
if (a .eq. 'D') then
read (*,*) i
write (*,*) a, i
endif
end
This should be enough to make the incremental strategy work if you compiler supports non-advancing input somehow.
The alternative is to read the letter plus the rest of the line into a large character buffer, then parse the buffer separately along the lines of
character a, buf(1024)
read (*,'(a1, a1024)') a, buf
if (a .eq. d) then
read (buf,*) i
endif