module inside if in verilog - if-statement

Question

i'm not that much in verilog
i'm trying to call a module inside if statement
i can't find the answer in google or may i didn't understand what should i do with MY CODE
my code is a full adder addition
i need the IF cause i want to add other things
this is my code:
module top (a,b,cin,Cout,Ctemp,sum,clk,X);
input [3:0] a,b;
input X;
input cin,clk;
output reg[3:0] sum;
output reg[2:0] Ctemp;
output reg Cout;
always#(posedge clk)
begin
generate
if (X==1)
add bit0(a[0], b[0], cin, sum[0], Ctemp[0]); //here i need to call add module
add bit1(a[1], b[1], Ctemp[0], sum[1], Ctemp[1]);
add bit2(a[2], b[2], Ctemp[1], sum[2], Ctemp[2]);
add bit3(a[3], b[3], Ctemp[2], sum[3], Cout);
end
endgenerate
endmodule
module add(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum = (~a*~b*cin)+(~a*b*~cin)+(a*~b*~cin)+(a*b*cin);
assign cout = (a*b)+(a*cin)+(b*cin);
endmodule

Answer 1

I'll give some hints. you need to move the module instantiations outside the always block (above or below). Then add additional wire declarations for for the outputs of the module that you will be flopping. I recommend modifying your module instantiation port connections to explicit (connect-by-name) instead of implicit (connect-by-order). This way even of the port order changes, the connectivity will be maintained. Extremely useful for modules with a lot of ports.
The body of your top module should looks something like this:
// ...
add bit3( .a(a[3]), .b(b[3]), .cin(Ctemp[2]), .sum(pre_sum[3]), .cout(pre_cout));
always#(posedge clk)
begin
if (X==1) begin
sum <= pre_sum;
Cout <= pre_cout;
end
end
Other recommendation: Use ANSI style module header; it is less typing and easier to maintain. Non-ANSI style was required for really old simulations before this century. Example:
module top (
input [3:0] a, b,
input cin,
output reg Cout,
output [2:0] Ctemp,
output reg [3:0] sum,
input clk,
input X );