My c++ application fails to link, and i don't know why - c++

I am currently getting back in to c++. I have been running into a problem building my application.
When i run make the output becomes:
g++ -c -Wall -I headers/ -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 -L/usr/local/lib -Wl,-rpath,/usr/local/lib -lSDL2 -lGL -lSDL2 -lSDL2main Debug.cpp -o Debug.o
g++ -c -Wall -I headers/ -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 -L/usr/local/lib -Wl,-rpath,/usr/local/lib -lSDL2 -lGL -lSDL2 -lSDL2main GameLoop.cpp -o GameLoop.o
g++ -c -Wall -I headers/ -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 -L/usr/local/lib -Wl,-rpath,/usr/local/lib -lSDL2 -lGL -lSDL2 -lSDL2main Main.cpp -o Main.o
g++ -c -Wall -I headers/ -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 -L/usr/local/lib -Wl,-rpath,/usr/local/lib -lSDL2 -lGL -lSDL2 -lSDL2main -o GAME Debug.o GameLoop.o Main.o
g++: warning: Debug.o: linker input file unused because linking not done
g++: warning: GameLoop.o: linker input file unused because linking not done
g++: warning: Main.o: linker input file unused because linking not done
The file structure of my project
Makefile
Main.cpp
GameLoop.cpp
Debug.cpp
headers/
Main.h
GameLoop.h
Debug.h
Makefile:
CC := g++
TARGET := GAME
SOURCES := $(wildcard *.cpp)
OBJECTS := $(patsubst %.cpp, %.o, $(SOURCES))
DEPS := $(wildcard headers/*.h)
CPPFLAGS := -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 $(shell sdl2-config --libs) -lGL -lSDL2 -lSDL2main
CFLAGS := -c -Wall -I headers/
##$(info OBJECTS= $(OBJECTS) :: SOURCES= $(SOURCES) :: EXECUTABLEOUT= $(TARGET))
default: $(TARGET)
%.o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $(CPPFLAGS) $< -c -o $#
$(TARGET): $(OBJECTS)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
RAW Paste Data
CC := g++
TARGET := GAME
SOURCES := $(wildcard *.cpp)
OBJECTS := $(patsubst %.cpp, %.o, $(SOURCES))
DEPS := $(wildcard headers/*.h)
CPPFLAGS := -I ../libs/inc/SDL2 -L ../libs/lib/SDL2 $(shell sdl2-config --libs) -lGL -lSDL2 -lSDL2main
CFLAGS := -c -Wall -I headers/
##$(info OBJECTS= $(OBJECTS) :: SOURCES= $(SOURCES) :: EXECUTABLEOUT= $(TARGET))
default: $(TARGET)
%.o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $(CPPFLAGS) $< -c -o $#
$(TARGET): $(OBJECTS)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
Currently been looking at over 60 answers on this page (and others) with no luck. :/

All your g++ calls use the -c option. From GCC's help:
-c Compile and assemble, but do not link
Your last g++ call should not have the -c option. The reason you have it is because you have specified it for all your CFLAGS:
CFLAGS := -c -Wall -I headers/
Removing it from there should fix your problem.

Remove the -c flag from the last line where you make the executable.
From Man page for g++:
-c Compile or assemble the source files, but do not link. The linking stage simply is not done. The ultimate output is in the form of an object file for each source file.

Related

linux C++ gmake "No rule to make target"

It's been a couple decades since I've had to manage makefiles. I've checked existing answers here, as well as googling elsewhere. When I use the target: $(BIN)/$(EXECUTABLE): $(OBJECTS)
I'm stumped as to why my makefile is failing with:
$ make
make: *** No rule to make target 'src/SRecord.o', needed by 'bin/main'. Stop.
Here's the Makefile:
# execute `make D='-g'` to make with debug symbols
DEFS := $(D)
CC := gcc $(DEFS)
CFLAGS := -std=c99 -Wall -Wextra
CXX := g++ $(DEFS)
CXXFLAGS := -std=c++17 -Wall -Wextra
BIN := bin
SRC := src
INCLUDE := include
LIB := lib
#LIBSOURCES := $(wildcard $(LIB)/*.cpp)
#LIBOBJECTS := $(LIBSOURCES:%.cpp=%.o)
#OBJECTS := $(subst $(LIB)/,,$(LIBOBJECTS))
SOURCES := $(wildcard $(SRC)/*.cpp)
OBJECTS := $(SOURCES:%.cpp=%.o)
# SOURCES := \
# $(SRC)/main.cpp \
# $(SRC)/SerialPort.cpp \
# $(SRC)/ShadowUpdate.cpp \
# $(SRC)/SRecord.cpp
# OBJECTS := \
# $(SRC)/SerialPort.o \
# $(SRC)/ShadowUpdate.o \
# $(SRC)/SRecord.o
EXECUTABLE := main
#
# Targets
#
.PHONY: clean all
all: $(BIN)/$(EXECUTABLE)
clean:
$(RM) $(BIN)/$(EXECUTABLE)
$(RM) $(OBJECTS)
run: all
./$(BIN)/$(EXECUTABLE)
# $(BIN)/$(EXECUTABLE): $(SRC)/*
$(BIN)/$(EXECUTABLE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -I$(INCLUDE) -L$(LIB) $^ -o $#
#
# Dependencies - must be at end of makefile
#
DEPDIR := .d
$(shell mkdir -p $(DEPDIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
POSTCOMPILE = #mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d && touch $#
%.o: %.c
%.o: %.c $(DEPDIR)/%.d
$(CC) -c -o $*.o $(DEPFLAGS) $(CFLAGS) $<
$(POSTCOMPILE)
%.o: %.cpp
%.o: %.cpp $(DEPDIR)/%.d
$(CXX) -c -o $*.o $(DEPFLAGS) $(CXXFLAGS) $<
$(POSTCOMPILE)
$(DEPDIR)/%.d: ;
.PRECIOUS: $(DEPDIR)/%.d
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SOURCES))))
It works with the commented out target: # $(BIN)/$(EXECUTABLE): $(SRC)/*
But, I want to be able to have a more complex project than simply listing all the source files as dependencies to the executable.
Here's my file tree:
src/
src/SerialPort.cpp
src/SRecord.cpp
src/ShadowUpdate.cpp
src/main.cpp
include
include/ShadowUpdate.h
include/SerialPort.h
include/SRecord.h
include/the_exo.h
bin/
bin/main
Makefile
lib/
.d/
The automatic dependency generation isn't working either, even though it is straight from GNU's website.
Think about what the % expands to in
%.o: %.cpp $(DEPDIR)/%.d
plugging in src/SRecord.o:
src/SRecord.o: src/SRecord.cpp .d/src/SRecord.d
Can you see the issue? Try the following instead
$(SRC)/%.o: $(SRC)/%.cpp $(SRC)/$(DEPDIR)/%.d
You won't need the lines that override the built-in recipes (%.o: %.cpp), get rid of them.
For clarity to anyone looking for the answer in the future, I'm posting my revised Makefile:
BIN := bin
SRC := src
INCLUDE := include
LIB := lib
# execute `make D='-g'` to make with debug symbols
DEFS := $(D)
CC := gcc $(DEFS)
CFLAGS := -I$(INCLUDE) -std=c99 -Wall -Wextra
CXX := g++ $(DEFS)
CXXFLAGS := -I$(INCLUDE) -std=c++17 -Wall -Wextra
#LIBSOURCES := $(wildcard $(LIB)/*.cpp)
#LIBOBJECTS := $(LIBSOURCES:%.cpp=%.o)
#OBJECTS := $(subst $(LIB)/,,$(LIBOBJECTS))
SOURCES := $(wildcard $(SRC)/*.cpp)
OBJECTS := $(SOURCES:%.cpp=%.o)
EXECUTABLE := main
#
# Targets
#
.PHONY: clean all
all: $(BIN)/$(EXECUTABLE)
clean:
$(RM) $(BIN)/$(EXECUTABLE)
$(RM) $(OBJECTS)
run: all
./$(BIN)/$(EXECUTABLE)
$(BIN)/$(EXECUTABLE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -L$(LIB) $^ -o $#
#
# Dependencies - must be at end of makefile
#
DEPDIR := $(SRC)/.d
$(shell mkdir -p $(DEPDIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
POSTCOMPILE = #mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d && touch $#
%.o: %.c
%.o: %.c $(DEPDIR)/%.d
$(CC) -c -o $# $(DEPFLAGS) $(CFLAGS) $<
$(POSTCOMPILE)
%.o: %.cpp
$(SRC)/%.o: $(SRC)/%.cpp $(DEPDIR)/%.d
$(CXX) -c -o $# $(DEPFLAGS) $(CXXFLAGS) $<
$(POSTCOMPILE)
$(DEPDIR)/%.d: ;
.PRECIOUS: $(DEPDIR)/%.d
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SOURCES))))
To clarify my comment to the above answer, if I comment out the "override" target (%.o: %.cpp), here's the output:
$ make clean; make
rm -f bin/main
rm -f src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/SRecord.o src/SRecord.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/SerialPort.o src/SerialPort.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/ShadowUpdate.o src/ShadowUpdate.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/main.o src/main.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -Llib src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o -o bin/main
Clearly, the dependencies are not being made. My rule was not executed.
But, with the empty %.o: %.cpp target in place, the make performs as expected:
$ make clean; make
rm -f bin/main
rm -f src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o
g++ -c -o src/SRecord.o -MT src/SRecord.o -MMD -MP -MF src/.d/SRecord.Td -Iinclude -std=c++17 -Wall -Wextra src/SRecord.cpp
g++ -c -o src/SerialPort.o -MT src/SerialPort.o -MMD -MP -MF src/.d/SerialPort.Td -Iinclude -std=c++17 -Wall -Wextra src/SerialPort.cpp
g++ -c -o src/ShadowUpdate.o -MT src/ShadowUpdate.o -MMD -MP -MF src/.d/ShadowUpdate.Td -Iinclude -std=c++17 -Wall -Wextra src/ShadowUpdate.cpp
g++ -c -o src/main.o -MT src/main.o -MMD -MP -MF src/.d/main.Td -Iinclude -std=c++17 -Wall -Wextra src/main.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -Llib src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o -o bin/main

Compile All source file in a directory and store objs in different directory

Following is my make file
CC = g++
CFLAGS = -Wall -c -fPIC
INCLUDES = -I${HOME}/ComingSoon/api/include
LFLAGs = -L${HOME}/ComingSoon/lib
LIB_DIR = ${HOME}/ComingSoon/lib
LIBS = -lapi
API_SRCDIR = ${HOME}/ComingSoon/api/source
API_SOURCE = $(wildcard ${HOME}/ComingSoon/api/source/*.cpp)
#API_SOURCE = $(shell find $(API_SRCDIR) -name '*.cpp')
API_OBJ_SOURCE = $(wildcard ${HOME}/ComingSoon/api/obj/*.o)
OBJS_DIR_API = ${HOME}/ComingSoon/api/obj/
OBJS = $(patsubst $(API_SRCDIR)/%.cpp,$(OBJS_DIR_API)%.o,$(API_SOURCE))
api: $(OBJS)
$(OBJS): $(API_SOURCE) Makefile
$(CC) $(CFLAGS) $(INCLUDES) $< -o $#
clean_api:
rm -rf ${HOME}/ComingSoon/lib/*.so
rm -rf ${HOME}/ComingSoon/api/obj/*.o
I want to complie all the source files in the source directory.
The make file is compiling as
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/multiply.o
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/add.o
But the output should be as follows
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/multiply.o
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/add.cpp -o /home/soumya/ComingSoon/api/obj/add.o
The makfile is compiling the same source file to make two different object file. Where I am doing wrong?
What should I use in place of
$(OBJS): $(API_SOURCE) Makefile
Your API_SOURCE variable contains multiply.cpp add.cpp, so your rule comes out to:
$(OBJS): multiply.cpp add.cpp Makefile
$(CC) ... $< -o $#
So $< always expands to multiply.cpp. The correct way is to write a pattern rule:
$(OBJS_DIR_API)%.o: $(API_SRCDIR)/%.cpp Makefile
$(CC) ... $< -o $#

What difference between my compilation line and my makefile could cause the error?

I have previously write a compilation line which is working.
Howewer, my Makefile, which generates more or less the same thing, isn't successfully compiling.
Command line (working) :
sh3eb-elf-gcc -m3 -mb -ffreestanding -nostdlib -T addin.ld src/crt0.s src/BTKOM.cpp src/bluetooth.cpp src/syscall.s -o addin.elf -Iinclude -L libs/ -lgcc -lmonochrome -lfx -O2 -fno-exceptions
Makefile :
CC = sh3eb-elf-gcc
SRCDIR = src
INCLDIR = include
LIBDIR = libs
EXTENSIONS = c cpp s
LIBS = -lgcc -lmonochrome -lfx
WFLAGS = -Wall
CFLAGS = -I $(INCLDIR) $(WFLAGS)
LFLAGS = -m3 -mb -ffreestanding -nostdlib -T addin.ld -L $(LIBDIR) $(LIBS) -O2 -fno-exceptions
SRCS := $(SRCS) $(foreach EXT,$(EXTENSIONS),$(wildcard $(SRCDIR)/*.$(EXT)))
OBJS := $(OBJS) $(foreach EXT,$(EXTENSIONS),$(patsubst $(SRCDIR)/%.$(EXT),%.o,$(wildcard $(SRCDIR)/*.$(EXT))))
OUT = addin
all : $(OUT).elf
$(OUT).elf : $(OBJS)
$(CC) $(LFLAGS) -o $# $^
$(OBJS) : $(SRCDIR)/$(SRCS)
$(CC) $(CFLAGS) -c $(SRCS)
clean:
rm -f *.o
cleaner:
rm -f *.o $(OUT).elf $(OUT).g1a $(OUT).bin
Generated lines from makefile :
sh3eb-elf-gcc -I include -Wall -c src/MonochromeLib.c src/BTKOM.cpp src/bluetooth.cpp src/syscall.s src/crt0.s
sh3eb-elf-gcc -m3 -mb -ffreestanding -nostdlib -T addin.ld -L libs -lgcc -lmonochrome -lfx -O2 -fno-exceptions -o addin.elf MonochromeLib.o BTKOM.o bluetooth.o syscall.o crt0.o
Output :
BTKOM.o: In function `_main':
BTKOM.cpp:(.text+0xc4): undefined reference to `_memset'
BTKOM.cpp:(.text+0xec): undefined reference to `_GetKey'
bluetooth.o: In function `Bluetooth::Bluetooth()':
bluetooth.cpp:(.text+0xa0): undefined reference to `_srand'
bluetooth.cpp:(.text+0xa4): undefined reference to `_rand'
bluetooth.cpp:(.text+0xac): undefined reference to `_memcpy'
...
There's a reason the built-in linking rule is defined as
$(LINK.o) $^ $(LOADLIBES) $(LDLIBS) -o $#
LINK.o is
$(CC) $(LDFLAGS) $(TARGET_ARCH)
You should find it works by rewriting your makefile as
LDLIBS := -lgcc -lmonochrome -lfx
LDFLAGS := -nostdlib -T addin.ld -L libs
$(OUT).elf: $(OBJS)
$(LINK.o) $^ $(LDLIBS) -o $#
Note that -O2, ffreestanding and -fno-exceptions are compilation options, not linking options (and I think -m3 and -mb are as well).

Unresolve External Symbol CUDA C++ (Kernel to Kernel Calls) [duplicate]

This is my first program using Dynamic Parallelism and I am unable to compile the code. I need to be able to run this for my research project at college and any help will be most appreciated:
I get the following error:
/cm/shared/apps/cuda50/toolkit/5.0.35/bin/nvcc -m64 -dc -gencode arch=compute_35,code=sm_35 -rdc=true -dlink -po maxrregcount=16 -I/cm/shared/apps/cuda50/toolkit/5.0.35 -I. -I.. -I../../common/inc -o BlackScholes.o -c BlackScholes.cu
g++ -m64 -I/cm/shared/apps/cuda50/toolkit/5.0.35 -I. -I.. -I../../common/inc -o BlackScholes_gold.o -c BlackScholes_gold.cpp
g++ -m64 -o BlackScholes BlackScholes.o BlackScholes_gold.o -L/cm/shared/apps/cuda50/toolkit/5.0.35/lib64 -lcudart -lcudadevrt
BlackScholes.o: In function `__sti____cudaRegisterAll_47_tmpxft_000059cb_00000000_6_BlackScholes_cpp1_ii_c58990ec()':
tmpxft_000059cb_00000000-3_BlackScholes.cudafe1.cpp:(.text+0x1354): undefined reference to `__cudaRegisterLinkedBinary_47_tmpxft_000059cb_00000000_6_BlackScholes_cpp1_ii_c58990ec'
collect2: ld returned 1 exit status
make: *** [BlackScholes] Error 1
I have one cpp file, one cu file and one cuh file. Important portions of my makefile are below:
# CUDA code generation flags
#GENCODE_SM10 := -gencode arch=compute_10,code=sm_10
GENCODE_SM20 := -gencode arch=compute_20,code=sm_20
GENCODE_SM30 := -gencode arch=compute_30,code=sm_30 -gencode arch=compute_35,code=sm_35
GENCODE_SM35 := -gencode arch=compute_35,code=sm_35
#GENCODE_FLAGS := $(GENCODE_SM10) $(GENCODE_SM20) $(GENCODE_SM30)
GENCODE_FLAGS := $(GENCODE_SM35)
# OS-specific build flags
ifneq ($(DARWIN),)
LDFLAGS := -Xlinker -rpath $(CUDA_LIB_PATH) -L$(CUDA_LIB_PATH) -lcudart -lcudadevrt
CCFLAGS := -arch $(OS_ARCH)
else
ifeq ($(OS_SIZE),32)
LDFLAGS := -L$(CUDA_LIB_PATH) -lcudart -lcudadevrt
CCFLAGS := -m32
else
LDFLAGS := -L$(CUDA_LIB_PATH) -lcudart -lcudadevrt
CCFLAGS := -m64
endif
endif
# OS-architecture specific flags
ifeq ($(OS_SIZE),32)
NVCCFLAGS := -m32 -dc
else
NVCCFLAGS := -m64 -dc
endif
# Debug build flags
ifeq ($(dbg),1)
CCFLAGS += -g
NVCCFLAGS += -g -G
TARGET := debug
else
TARGET := release
endif
# Common includes and paths for CUDA
INCLUDES := -I$(CUDA_INC_PATH) -I. -I.. -I../../common/inc
# Additional parameters
MAXRREGCOUNT := -po maxrregcount=16
# Target rules
all: build
build: BlackScholes
BlackScholes.o: BlackScholes.cu
$(NVCC) $(NVCCFLAGS) $(EXTRA_NVCCFLAGS) $(GENCODE_FLAGS) -rdc=true -dlink $(MAXRREGCOUNT) $(INCLUDES) -o $# -c $<
BlackScholes_gold.o: BlackScholes_gold.cpp
$(GCC) $(CCFLAGS) $(INCLUDES) -o $# -c $<
BlackScholes: BlackScholes.o BlackScholes_gold.o
$(GCC) $(CCFLAGS) -o $# $+ $(LDFLAGS) $(EXTRA_LDFLAGS)
mkdir -p ../../bin/$(OSLOWER)/$(TARGET)
cp $# ../../bin/$(OSLOWER)/$(TARGET)
enter code here
run: build
./BlackScholes
When using the host linker (g++) for final linking of your executable, and when using relocatable device code (nvcc -dc), it's necessary to do an intermediate device code link step.
From the documentation:
If you want to invoke the device and host linker separately, you can do:
nvcc –arch=sm_20 –dc a.cu b.cu
nvcc –arch=sm_20 –dlink a.o b.o –o link.o
g++ a.o b.o link.o –L<path> -lcudart
Since you are specifying -dc on the compile line, you are getting a compile-only operation (just as if you had specified -c to g++).
Here's a modified/condensed Makefile that should show you what is involved:
GENCODE_SM35 := -gencode arch=compute_35,code=sm_35
GENCODE_FLAGS := $(GENCODE_SM35)
LDFLAGS := -L/usr/local/cuda/lib64 -lcudart -lcudadevrt
CCFLAGS := -m64
NVCCFLAGS := -m64 -dc
NVCC := nvcc
GCC := g++
# Debug build flags
ifeq ($(dbg),1)
CCFLAGS += -g
NVCCFLAGS += -g -G
TARGET := debug
else
TARGET := release
endif
# Common includes and paths for CUDA
INCLUDES := -I/usr/local/cuda/include -I. -I..
# Additional parameters
MAXRREGCOUNT := -po maxrregcount=16
# Target rules
all: build
build: BlackScholes
BlackScholes.o: BlackScholes.cu
$(NVCC) $(NVCCFLAGS) $(EXTRA_NVCCFLAGS) $(GENCODE_FLAGS) $(MAXRREGCOUNT) $(INCLUDES) -o $# $<
$(NVCC) -dlink $(GENCODE_FLAGS) $(MAXRREGCOUNT) -o bs_link.o $#
BlackScholes_gold.o: BlackScholes_gold.cpp
$(GCC) $(CCFLAGS) $(INCLUDES) -o $# -c $<
BlackScholes: BlackScholes.o BlackScholes_gold.o bs_link.o
$(GCC) $(CCFLAGS) -o $# $+ $(LDFLAGS) $(EXTRA_LDFLAGS)
run: build
./BlackScholes

C++ Makefile missing separator in .dep

On OS X Mavericks i am trying to build a project using the following Makefile:
CC=g++
EXECUTABLE=minigi
SRC_DIR=src
INTERM_DIR=obj
INCLUDES=-I $(SRC_DIR) -I /usr/local/Cg/examples/OpenGL/glew/include/
LIBS=-L/usr/local/lang/NVIDIA_GPU_Computing_SDK/sdk/C/common/lib/linux/ -lpng -stdc++ -lGL -lGLU -lGLEW -lSDLmain -lSDL -lgomp
CFLAGS_COMMON=$(INCLUDES)
CFLAGS=$(CFLAGS_COMMON) -O3 -DNDEBUG -fopenmp
#CFLAGS=$(CFLAGS_COMMON) -g -O0 -D_DEBUG
SOURCE_FILES=$(shell find $(SRC_DIR) -iname '*.cpp')
DEP_FILES=$(SOURCE_FILES:$(SRC_DIR)/%.cpp=./$(INTERM_DIR)/%.dep)
OBJ_FILES=$(SOURCE_FILES:$(SRC_DIR)/%.cpp=./$(INTERM_DIR)/%.o)
all: $(EXECUTABLE)
clean:
rm -rf obj $(EXECUTABLE)
.PHONY: clean all
.SUFFIXES:
.SUFFIXES:.o .dep .cpp .h
$(INTERM_DIR)/%.dep: $(SRC_DIR)/%.cpp
mkdir -p `dirname $#`
printf `dirname $#`/ > $#
$(CC) $(CFLAGS_COMMON) $< -MM | sed -r -e 's,^(.*)\.o\s*\:,\1.o $# :,g' >> $#
ifneq ($(MAKECMDGOALS),clean)
-include $(DEP_FILES)
endif
$(INTERM_DIR)/%.o: $(SRC_DIR)/%.cpp
mkdir -p $(INTERM_DIR)
$(CC) $(CFLAGS) -c $< -o $#
$(EXECUTABLE): $(OBJ_FILES)
$(CC) $^ $(LIBS) -o $#
However, when I type make I get the following error:
obj/app/sdl_gl_appliacation.dep:1: *** missing separator. Stop.
The file obj/app/sdl_gl_application.dep looks as follows:
-n obj/app/
As I know very little about makefiles (and did not write the posted one) every help would be appreciated.
P.S.
I modified the line printf dirname $#/ > $# . In the original file there was an echo -n but that is not working on OS X.
Well, let's clean this up a little bit.
The way the dependencies are handled really is ugly, GCC can do it for you automatically.
EXECUTABLE := minigi
SRC_DIR := src
OBJ_DIR := obj
SRC_FILES := $(wildcard $(SRC_DIR)/*.cpp)
OBJ_FILES := $(SRC_FILES:$(SRC_DIR)/%.cpp=$(OBJ_DIR)/%.o)
DEP_FILES := $(OBJ_FILES:.o=.d)
LDLIBS := -lpng -lstdc++ -lGL -lGLU -lGLEW -lSDLmain -lSDL -lgomp
LDFLAGS := -L/usr/local/lang/NVIDIA_GPU_Computing_SDK/sdk/C/common/lib/linux/
CPPFLAGS := -MMD -MP -DNDEBUG -fopenmp -I $(SRC_DIR) -I /usr/local/Cg/examples/OpenGL/glew/include/
CXXFLAGS := -O3
.PHONY: all clean
all: $(EXECUTABLE)
clean:
$(RM) -r $(OBJ_DIR) $(EXECUTABLE)
$(EXECUTABLE): $(OBJ_FILES)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp | $(OBJ_DIR)
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -o $# -c $<
$(OBJ_DIR):
mkdir $#
ifeq "$(MAKECMDGOALS)" ""
-include $(DEP_FILES)
endif
Some quick notes :
You're using C++, so you should use $(CXX) instead of $(CC) which is used for C code.
Along with this, you should use $(CXXFLAGS) instead of $(CFLAGS).
$(CPPFLAGS) is meant for preprocessor flags (-I, -D, or -fopenmp which is a compile-time flag).
-MMD -MP preprocessor flags will auto-generate dependency files when compiling. Learn more.
$(LDFLAGS) is meant for linker flags such as -L flags.
$(LDLIBS) is meant for linker libs such as -l flags
Avoid using the $(shell ) function since it will be executed every time the variable is expanded when assigned with the = operator instead of the := operator. $(wildcard ) is more suited for the job of listing files.