I have the following makefile that I use to build a program (a kernel, actually) that I'm working on. Its from scratch and I'm learning about the process, so its not perfect, but I think its powerful enough at this point for my level of experience writing makefiles.
AS = nasm
CC = gcc
LD = ld
TARGET = core
BUILD = build
SOURCES = source
INCLUDE = include
ASM = assembly
VPATH = $(SOURCES)
CFLAGS = -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions \
-nostdinc -fno-builtin -I $(INCLUDE)
ASFLAGS = -f elf
#CFILES = core.c consoleio.c system.c
CFILES = $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
SFILES = assembly/start.asm
SOBJS = $(SFILES:.asm=.o)
COBJS = $(CFILES:.c=.o)
OBJS = $(SOBJS) $(COBJS)
build : $(TARGET).img
$(TARGET).img : $(TARGET).elf
c:/python26/python.exe concat.py stage1 stage2 pad.bin core.elf floppy.img
$(TARGET).elf : $(OBJS)
$(LD) -T link.ld -o $# $^
$(SOBJS) : $(SFILES)
$(AS) $(ASFLAGS) $< -o $#
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
#Clean Script - Should clear out all .o files everywhere and all that.
clean:
-del *.img
-del *.o
-del assembly\*.o
-del core.elf
My main issue with this makefile is that when I modify a header file that one or more C files include, the C files aren't rebuilt. I can fix this quite easily by having all of my header files be dependencies for all of my C files, but that would effectively cause a complete rebuild of the project any time I changed/added a header file, which would not be very graceful.
What I want is for only the C files that include the header file I change to be rebuilt, and for the entire project to be linked again. I can do the linking by causing all header files to be dependencies of the target, but I cannot figure out how to make the C files be invalidated when their included header files are newer.
I've heard that GCC has some commands to make this possible (so the makefile can somehow figure out which files need to be rebuilt) but I can't for the life of me find an actual implementation example to look at. Can someone post a solution that will enable this behavior in a makefile?
EDIT: I should clarify, I'm familiar with the concept of putting the individual targets in and having each target.o require the header files. That requires me to be editing the makefile every time I include a header file somewhere, which is a bit of a pain. I'm looking for a solution that can derive the header file dependencies on its own, which I'm fairly certain I've seen in other projects.
As already pointed out elsewhere on this site, see this page:
Auto-Dependency Generation
In short, gcc can automatically create .d dependency files for you, which are mini makefile fragments containing the dependencies of the .c file you compiled.
Every time you change the .c file and compile it, the .d file will be updated.
Besides adding the -M flag to gcc, you'll need to include the .d files in the makefile (like Chris wrote above).
There are some more complicated issues in the page which are solved using sed, but you can ignore them and do a "make clean" to clear away the .d files whenever make complains about not being able to build a header file that no longer exists.
You could add a 'make depend' command as others have stated but why not get gcc to create dependencies and compile at the same time:
DEPS := $(COBJS:.o=.d)
-include $(DEPS)
%.o: %.c
$(CC) -c $(CFLAGS) -MM -MF $(patsubst %.o,%.d,$#) -o $# $<
The '-MF' parameter specifies a file to store the dependencies in.
The dash at the start of '-include' tells Make to continue when the .d file doesn't exist (e.g. on first compilation).
Note there seems to be a bug in gcc regarding the -o option. If you set the object filename to say obj/_file__c.o then the generated _file_.d will still contain _file_.o, not obj/_file_c.o.
This is equivalent to Chris Dodd's answer, but uses a different naming convention (and coincidentally doesn't require the sed magic. Copied from a later duplicate.
If you are using a GNU compiler, the compiler can assemble a list of dependencies for you. Makefile fragment:
depend: .depend
.depend: $(SOURCES)
rm -f ./.depend
$(CC) $(CFLAGS) -MM $^>>./.depend;
include .depend
There is also the tool makedepend, but I never liked it as much as gcc -MM
You'll have to make individual targets for each C file, and then list the header file as a dependency. You can still use your generic targets, and just place the .h dependencies afterwards, like so:
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
foo.c: bar.h
# And so on...
Basically, you need to dynamically create the makefile rules to rebuild the object files when the header files change. If you use gcc and gnumake, this is fairly easy; just put something like:
$(OBJDIR)/%.d: %.c
$(CC) -MM -MG $(CPPFLAGS) $< | sed -e 's,^\([^:]*\)\.o[ ]*:,$(#D)/\1.o $(#D)/\1.d:,' >$#
ifneq ($(MAKECMDGOALS),clean)
include $(SRCS:%.c=$(OBJDIR)/%.d)
endif
in your makefile.
Over and above what #mipadi said, you can also explore the use of the '-M' option to generate a record of the dependencies. You might even generate those into a separate file (perhaps 'depend.mk') which you then include in the makefile. Or you can find a 'make depend' rule which edits the makefile with the correct dependencies (Google terms: "do not remove this line" and depend).
Simpler solution: Just use the Makefile to have the .c to .o compilation rule be dependent on the header file(s) and whatever else is relevant in your project as a dependency.
E.g., in the Makefile somewhere:
DEPENDENCIES=mydefs.h yourdefs.h Makefile GameOfThrones.S07E01.mkv
::: (your other Makefile statements like rules
::: for constructing executables or libraries)
# Compile any .c to the corresponding .o file:
%.o: %.c $(DEPENDENCIES)
$(CC) $(CFLAGS) -c -o $# $<
None of the answers worked for me. E.g. Martin Fido's answer suggests gcc can create dependency file, but when I tried that it was generating empty (zero bytes) object files for me without any warnings or errors. It might be a gcc bug. I am on
$ gcc --version gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-16)
So here's my complete Makefile that works for me; it's a combination of solutions + something that wasn't mentioned by anyone else (e.g. "suffix replacement rule" specified as .cc.o:):
CC = g++
CFLAGS = -Wall -g -std=c++0x
INCLUDES = -I./includes/
# LFLAGS = -L../lib
# LIBS = -lmylib -lm
# List of all source files
SRCS = main.cc cache.cc
# Object files defined from source files
OBJS = $(SRCS:.cc=.o)
# # define the executable file
MAIN = cache_test
#List of non-file based targets:
.PHONY: depend clean all
## .DEFAULT_GOAL := all
# List of dependencies defined from list of object files
DEPS := $(OBJS:.o=.d)
all: $(MAIN)
-include $(DEPS)
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
#suffix replacement rule for building .o's from .cc's
#build dependency files first, second line actually compiles into .o
.cc.o:
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
clean:
$(RM) *.o *~ $(MAIN) *.d
Notice I used .cc .. The above Makefile is easy to adjust for .c files.
Also notice importance of these two lines :
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
so gcc is called once to build a dependency file first, and then actually compiles a .cc file. And so on for each source file.
I believe the mkdep command is what you want. It actually scans .c files for #include lines and creates a dependency tree for them. I believe Automake/Autoconf projects use this by default.
I'm developing a parallel project with a Main.cpp and a set of .hpp files. I've found the Makefile below suitable to compile, deploy and execute my project on a Xeon Phi. The problem here is that if I edit only one of the .hpp (so not Main.cpp) then when I execute make compile obviously nothing happens (so I have to execute make clean before). Can you help me to change it so if I edit file.hpp then it will compile it? Thanks!
FF_ROOT = /home/luca/fastflow
BOOST_ROOT = /home/luca/boost_1_59_0
CC = icpc -mmic
CXX = $(CC) -std=c++11 -DNO_DEFAULT_MAPPING
INCLUDES = -I $(BOOST_ROOT) -I $(FF_ROOT)
CXXFLAGS =
LDFLAGS = -pthread
OPTFLAGS = -O3 -finline-functions -DNDEBUG -g -O0
TARGETS = \
Main \
.PHONY: all clean copy exec cleanall
.SUFFIXES: .cpp
%: %.cpp
$(CXX) $(CXXFLAGS) $(INCLUDES) $(OPTFLAGS) -o $# $< $(LDFLAGS)
all: compile
compile: $(TARGETS)
copy:
scp $(TARGETS) mic0:
exec:
ssh mic0 './$(TARGETS) $(ARGS)'
clean:
rm -f $(TARGETS)
cleanall : clean
\rm -f *.o *~
Your Makefile is blatantly not sufficient. At the moment it only contains the commands to translate from one input to the next, but it's missing the crucial ingredient of any build system: Dependencies.
Dependencies are hard to maintain by hand. You could add main: a.hpp b.hpp etc by hand, but that doesn't scale and you forget to update it when you refactor. That's why make is not usually something the user should use directly. make is a bit like assembler: it's the final level at which build rules are expressed, but creating the build rules is best left to a higher-level system (e.g. automake or cmake or any of the other competitors in the field; or even the old makedepend).
As a side note, you really don't want to build the binary directly from source, that defeats almost all points of having a Makefile. You really want to break your project into separately compiled translation units, so that you only rebuild the minimal amount after a change.
OBJS := a.o b.o c.o
main: $(OBJS)
$(CXX) $(CXXFLAGS) $(LDFLAGS) $< -o $#
.cc.o:
$(CXX) $(CXXFLAGS) -c $< -o $#
# Dependencies! This is in addition to the implied "foo.o: foo.cc" above.
a.o: a.h b.h tools.h
b.o: b.h tools.h
c.o: c.h b.h weirdstuff.h
Many tutorials explain all this.
Add a rule for the source file where it depends on all (local, not system) header files.
Like
Main.cpp: SomeHeaderFile.hpp SomeOtherHeaderFile.hpp
I am new in make file.
I have a program made of
main.cpp
types.hpp
application/coordinator.hpp
application/correlation.hpp
application/handler.hpp
application/settings.hpp
libraries/basket.hpp
libraries/config.hpp
libraries/graphics.hpp
...
I have so many files and the list of my files will be updated so many times. I want the make file recognizes automatically which .o file to be generated or updated. I don't want to update my make file each time I create and include a new file. The output must be generated in a directory called bin
main.cpp is my only cpp file and the rest of my files are hpp.
Till now, this link has inspired me to write this code:
CC=g++
CFLAGS= -g -Wfatal-errors
CFLAGS+= -std=c++11
LIBS= -lboost_filesystem -lboost_system
all: run
run: $(OBJS)
$(CC) $(CFLAGS) $^ main.cpp -o $#
$(OBJS): bin/%.o : bin/%.hpp
How to improve it to working code and what I want?
If you intend to only ever have one cpp file, you could write the makefile in the following way:
CXX := g++
CXXFLAGS := -g -Wall -pedantic -Wextra
HEADERS := types.hpp $(wildcard application/*.hpp) $(wildcard libraries/*.hpp)
all: run
run: main.cpp $(HEADERS)
$(CXX) $(CXXFLAGS) $< -o $#
$(wildcard) will find all headers in application and libraries. The executable will depend on all the headers and main.cpp so if any of them changes, the binary will be rebuilt.
$< means "first dependency". This way, only the cpp file is passed to the compiler.
Note: in GNU make conventions, CC and CFLAGS refer to the C compiler. For C++, the variables are named CXX and CXXFLAGS.
Here's a different scheme: generate the dependency information while you build the software. This works with multiple cpp files creating multiple object files.
CXX := g++
#CPPFLAGS := preprocessor flags, e.g. -I and -D
CXXFLAGS := -g -Wall -pedantic -Wextra -Wfatal-errors -std=c++11 -MD -MP
SOURCES := main.cpp
OBJECTS := $(SOURCES:.cpp=.o)
DEPFILES:= $(OBJECTS:.o=.d)
all: run
# Link the executable
run: $(OBJECTS)
$(CXX) $(LDFLAGS) $^ -o $# $(LIBS)
-include $(DEPFILES)
When .o files are built, the -MD -MP flags tell the compiler to generate the dependency file as a side-effect. These dependency files are included into the makefile if they are present.
This uses GNU make's built-in %.o : %.cpp rule. We just supply parameters to it (CXX, CPPFLAGS, CXXFLAGS).
Make already knows to rebuild .o files if the corresponding .cpp file is newer (either GNU make's built-in rule or a hand-written one). With .d files included into the makefile, we tell make that the object file also depends on the header files and should be rebuilt when one of them changes. But the rule to rebuild the .o is always %.o : %.cpp
My makefile compiles our C++ code without any problems but it can not create object files.
How do I need to modify this file in order to create the object file for each .cpp file?
Is there any problem if I proceed without creating an object file for each .cpp file ?
My makefile looks like this:
engine:main.cpp correlation.cpp correlation.h matcher.cpp matcher.h scheduler.cpp scheduler.h parser.cpp parser.h cache_manager.cpp cache_manager.h init.cpp init.h db_manager.cpp db_manager.h
g++ -o engine main.cpp correlation.cpp correlation.h matcher.cpp matcher.h scheduler.cpp scheduler.h parser.cpp parser.h cache_manager.cpp cache_manager.h init.cpp init.h db_manager.cpp db_manager.h -lpthread -lboost_regex -I/usr/include -ggdb \
-I/usr/include/oracle/11.1/client \
-L$(ORACLE_HOME)/lib -lclntsh -locci
clean:
rm -f engine
There's no problem if you skip naming object files. They'll still be created behind the scenes though.
The advantage of specifically creating object files is that you'll save time recompiling, since make will be able to skip any object file it doesn't have to recreate (since it's up-to-date; something that won't work with temporary files as they're deleted).
The easiest way to get this working is by using a special placeholder syntax in your makefile:
%.o: %.cpp
g++ -c -o $# $< $(YOUR_OTHER_PARAMS)
In this example you define a generic recipe for any file ending in .o to requiring a file with the same name ending in .cpp. $# is a special macro that will expand to the current output file, while $< will include the current input file.
In a similar way you may define macros for other files as well:
%.png: %.bmp
myinmageconverter -png $< $#
You can still name specific recipes, e.g. for cases where one specific file needs additional or different parameters. Just name it in your makefile as usual. The placeholder syntax will only try to match otherwise unmatched targets.
If you'd like to mention some generic or precompiled header, you can still include it (just like any other dependency):
%.o: %.cpp common.hpp
g++ -c -o $# $< $(YOUR_OTHER_PARAMS)
For the actual executable, you can then just define your components as usual, i.e. your example could look like this:
engine: main.o correlation.o matcher.o scheduler.o ...
g++ -o engine main.o correlation. matcher.o ...
%.o: %.cpp
g++ -c -o $# $< -lpthread -lboost_regex -I/usr/include -ggdb ...
I am having compiling errors. I have one cpp file and many headers. For the makefile I thought I needed to list all the headers file. The LinkedBinaryTree.h contains includes for all the other header files. This what I wrote:
all: hw4a
hw4a: LinkedBinaryTree.cpp linkedBinaryTree.h booster.h arrayQueue. binaryTree.h binaryTreeNode.h myExceptions.h queue.h
g++ -o hw4a LinkedBinaryTree.cpp LinkedBinaryTree.h booster.h arrayQueue.h binaryTree.h binaryTreeNode.h myExceptions.h queue.h
clean:
rm hw4a
I was told that O just needed to do:
g++ LinkedBinaryTree.cpp -o bst.exe
Which one is correct?
The latter is correct: g++ -o result.exe source.cpp. You must not include header files in the compiler command, since they are automatically included by the preprocessor already.
Of course the header files are still dependencies and must be listed in the makefile. That's why there is a special universal syntax to refer to the first reference only:
.phony: all clean
all: result.exe
result.exe: main.o
$(CXX) -o $# $+
main.o: main.cpp class1.hpp lib2.hpp
$(CXX) -c -o $# $<
The $+ means "all dependecies" (with repetition; $^ also expands to all dependencies but uniquified), as you need for linking, while $< only means "first dependency", as you need for compiling.
While you're at it, sprinkle generous warning flags over your compiler commands.
What you were told. Includes should be included, not being compiled as separate units.