I am new in make file.
I have a program made of
main.cpp
types.hpp
application/coordinator.hpp
application/correlation.hpp
application/handler.hpp
application/settings.hpp
libraries/basket.hpp
libraries/config.hpp
libraries/graphics.hpp
...
I have so many files and the list of my files will be updated so many times. I want the make file recognizes automatically which .o file to be generated or updated. I don't want to update my make file each time I create and include a new file. The output must be generated in a directory called bin
main.cpp is my only cpp file and the rest of my files are hpp.
Till now, this link has inspired me to write this code:
CC=g++
CFLAGS= -g -Wfatal-errors
CFLAGS+= -std=c++11
LIBS= -lboost_filesystem -lboost_system
all: run
run: $(OBJS)
$(CC) $(CFLAGS) $^ main.cpp -o $#
$(OBJS): bin/%.o : bin/%.hpp
How to improve it to working code and what I want?
If you intend to only ever have one cpp file, you could write the makefile in the following way:
CXX := g++
CXXFLAGS := -g -Wall -pedantic -Wextra
HEADERS := types.hpp $(wildcard application/*.hpp) $(wildcard libraries/*.hpp)
all: run
run: main.cpp $(HEADERS)
$(CXX) $(CXXFLAGS) $< -o $#
$(wildcard) will find all headers in application and libraries. The executable will depend on all the headers and main.cpp so if any of them changes, the binary will be rebuilt.
$< means "first dependency". This way, only the cpp file is passed to the compiler.
Note: in GNU make conventions, CC and CFLAGS refer to the C compiler. For C++, the variables are named CXX and CXXFLAGS.
Here's a different scheme: generate the dependency information while you build the software. This works with multiple cpp files creating multiple object files.
CXX := g++
#CPPFLAGS := preprocessor flags, e.g. -I and -D
CXXFLAGS := -g -Wall -pedantic -Wextra -Wfatal-errors -std=c++11 -MD -MP
SOURCES := main.cpp
OBJECTS := $(SOURCES:.cpp=.o)
DEPFILES:= $(OBJECTS:.o=.d)
all: run
# Link the executable
run: $(OBJECTS)
$(CXX) $(LDFLAGS) $^ -o $# $(LIBS)
-include $(DEPFILES)
When .o files are built, the -MD -MP flags tell the compiler to generate the dependency file as a side-effect. These dependency files are included into the makefile if they are present.
This uses GNU make's built-in %.o : %.cpp rule. We just supply parameters to it (CXX, CPPFLAGS, CXXFLAGS).
Make already knows to rebuild .o files if the corresponding .cpp file is newer (either GNU make's built-in rule or a hand-written one). With .d files included into the makefile, we tell make that the object file also depends on the header files and should be rebuilt when one of them changes. But the rule to rebuild the .o is always %.o : %.cpp
Related
I have the following makefile that I use to build a program (a kernel, actually) that I'm working on. Its from scratch and I'm learning about the process, so its not perfect, but I think its powerful enough at this point for my level of experience writing makefiles.
AS = nasm
CC = gcc
LD = ld
TARGET = core
BUILD = build
SOURCES = source
INCLUDE = include
ASM = assembly
VPATH = $(SOURCES)
CFLAGS = -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions \
-nostdinc -fno-builtin -I $(INCLUDE)
ASFLAGS = -f elf
#CFILES = core.c consoleio.c system.c
CFILES = $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
SFILES = assembly/start.asm
SOBJS = $(SFILES:.asm=.o)
COBJS = $(CFILES:.c=.o)
OBJS = $(SOBJS) $(COBJS)
build : $(TARGET).img
$(TARGET).img : $(TARGET).elf
c:/python26/python.exe concat.py stage1 stage2 pad.bin core.elf floppy.img
$(TARGET).elf : $(OBJS)
$(LD) -T link.ld -o $# $^
$(SOBJS) : $(SFILES)
$(AS) $(ASFLAGS) $< -o $#
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
#Clean Script - Should clear out all .o files everywhere and all that.
clean:
-del *.img
-del *.o
-del assembly\*.o
-del core.elf
My main issue with this makefile is that when I modify a header file that one or more C files include, the C files aren't rebuilt. I can fix this quite easily by having all of my header files be dependencies for all of my C files, but that would effectively cause a complete rebuild of the project any time I changed/added a header file, which would not be very graceful.
What I want is for only the C files that include the header file I change to be rebuilt, and for the entire project to be linked again. I can do the linking by causing all header files to be dependencies of the target, but I cannot figure out how to make the C files be invalidated when their included header files are newer.
I've heard that GCC has some commands to make this possible (so the makefile can somehow figure out which files need to be rebuilt) but I can't for the life of me find an actual implementation example to look at. Can someone post a solution that will enable this behavior in a makefile?
EDIT: I should clarify, I'm familiar with the concept of putting the individual targets in and having each target.o require the header files. That requires me to be editing the makefile every time I include a header file somewhere, which is a bit of a pain. I'm looking for a solution that can derive the header file dependencies on its own, which I'm fairly certain I've seen in other projects.
As already pointed out elsewhere on this site, see this page:
Auto-Dependency Generation
In short, gcc can automatically create .d dependency files for you, which are mini makefile fragments containing the dependencies of the .c file you compiled.
Every time you change the .c file and compile it, the .d file will be updated.
Besides adding the -M flag to gcc, you'll need to include the .d files in the makefile (like Chris wrote above).
There are some more complicated issues in the page which are solved using sed, but you can ignore them and do a "make clean" to clear away the .d files whenever make complains about not being able to build a header file that no longer exists.
You could add a 'make depend' command as others have stated but why not get gcc to create dependencies and compile at the same time:
DEPS := $(COBJS:.o=.d)
-include $(DEPS)
%.o: %.c
$(CC) -c $(CFLAGS) -MM -MF $(patsubst %.o,%.d,$#) -o $# $<
The '-MF' parameter specifies a file to store the dependencies in.
The dash at the start of '-include' tells Make to continue when the .d file doesn't exist (e.g. on first compilation).
Note there seems to be a bug in gcc regarding the -o option. If you set the object filename to say obj/_file__c.o then the generated _file_.d will still contain _file_.o, not obj/_file_c.o.
This is equivalent to Chris Dodd's answer, but uses a different naming convention (and coincidentally doesn't require the sed magic. Copied from a later duplicate.
If you are using a GNU compiler, the compiler can assemble a list of dependencies for you. Makefile fragment:
depend: .depend
.depend: $(SOURCES)
rm -f ./.depend
$(CC) $(CFLAGS) -MM $^>>./.depend;
include .depend
There is also the tool makedepend, but I never liked it as much as gcc -MM
You'll have to make individual targets for each C file, and then list the header file as a dependency. You can still use your generic targets, and just place the .h dependencies afterwards, like so:
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
foo.c: bar.h
# And so on...
Basically, you need to dynamically create the makefile rules to rebuild the object files when the header files change. If you use gcc and gnumake, this is fairly easy; just put something like:
$(OBJDIR)/%.d: %.c
$(CC) -MM -MG $(CPPFLAGS) $< | sed -e 's,^\([^:]*\)\.o[ ]*:,$(#D)/\1.o $(#D)/\1.d:,' >$#
ifneq ($(MAKECMDGOALS),clean)
include $(SRCS:%.c=$(OBJDIR)/%.d)
endif
in your makefile.
Over and above what #mipadi said, you can also explore the use of the '-M' option to generate a record of the dependencies. You might even generate those into a separate file (perhaps 'depend.mk') which you then include in the makefile. Or you can find a 'make depend' rule which edits the makefile with the correct dependencies (Google terms: "do not remove this line" and depend).
Simpler solution: Just use the Makefile to have the .c to .o compilation rule be dependent on the header file(s) and whatever else is relevant in your project as a dependency.
E.g., in the Makefile somewhere:
DEPENDENCIES=mydefs.h yourdefs.h Makefile GameOfThrones.S07E01.mkv
::: (your other Makefile statements like rules
::: for constructing executables or libraries)
# Compile any .c to the corresponding .o file:
%.o: %.c $(DEPENDENCIES)
$(CC) $(CFLAGS) -c -o $# $<
None of the answers worked for me. E.g. Martin Fido's answer suggests gcc can create dependency file, but when I tried that it was generating empty (zero bytes) object files for me without any warnings or errors. It might be a gcc bug. I am on
$ gcc --version gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-16)
So here's my complete Makefile that works for me; it's a combination of solutions + something that wasn't mentioned by anyone else (e.g. "suffix replacement rule" specified as .cc.o:):
CC = g++
CFLAGS = -Wall -g -std=c++0x
INCLUDES = -I./includes/
# LFLAGS = -L../lib
# LIBS = -lmylib -lm
# List of all source files
SRCS = main.cc cache.cc
# Object files defined from source files
OBJS = $(SRCS:.cc=.o)
# # define the executable file
MAIN = cache_test
#List of non-file based targets:
.PHONY: depend clean all
## .DEFAULT_GOAL := all
# List of dependencies defined from list of object files
DEPS := $(OBJS:.o=.d)
all: $(MAIN)
-include $(DEPS)
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
#suffix replacement rule for building .o's from .cc's
#build dependency files first, second line actually compiles into .o
.cc.o:
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
clean:
$(RM) *.o *~ $(MAIN) *.d
Notice I used .cc .. The above Makefile is easy to adjust for .c files.
Also notice importance of these two lines :
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
so gcc is called once to build a dependency file first, and then actually compiles a .cc file. And so on for each source file.
I believe the mkdep command is what you want. It actually scans .c files for #include lines and creates a dependency tree for them. I believe Automake/Autoconf projects use this by default.
I am stuck, writing my Makefile.
Directory structure:
.\
Makefile
.\src\*.cpp(s)
.\bin
Desire: What I want to achieve with one Makefile.
Run: make
Output (Terminal):
g++ -g -Wall -c -o src/program1.o src/program1.cpp
g++ -g -Wall -c -o src/program2.o src/program2.cpp
g++ -g -Wall -c -o src/program3.o src/program3.cpp
g++ -g -Wall -c -o src/program4.o src/program4.cpp
Output (in /bin/)
program1.exe
program2.exe
program3.exe
program4.exe
EDIT:
CXX = g++
CXXFLAGS = -Wall -g3 -O0
SRC := ${wildcard src/*.cpp}
OBJS := $(SRC:.cpp=.o)
BIN := $(SRC:src/%.cpp=bin/%)
.PHONY: all
all: $(BIN)
$(BIN): $(OBJS)
$(CXX) -c $(CXXFLAGS) -o $(OBJS)
bin/%: src/%.o
$(CXX) -o $# $^
Error:
g++: warning: linker input file unused because linking not done
The introductory parts of the GNU make manual describe that all: $(BIN) creates a target all that depends on a target bin. That means make will try to create bin. Then you have $(BIN): $(OBJS) which says bin depends on all the object files, so make will try to create all the object files. Then there's a recipe for that rule that says, after you've created the object files run this command, which links together all the object files into a single program (bin).
So make is doing exactly what you asked it to do.
The problem is that is apparently not what you want it to do.
In your question you write, then take the original filenames of each *.cpp and add that to the executable which I don't fully understand, but I assumed that you want to link all the objects into a single executable, which is what your makefile does.
But then later you write: How can I output to bin directory and generate the correct executables?, but you never define what "correct executables" means, and this makes it sound like you want to turn each individual object file into its own executable; that's clearly not what your makefile does.
So before you can tell make what you want, first you have understand clearly what you want so you can write it in your makefile. And if you need us to help you write it into your makefile, you need to explain it clearly in your question so we can understand it.
Cheers!
ETA
OK so you want every source file to compile into an object file, then every object file to compile to a separate binary.
First compute the names of all the binaries you want to build:
SRCS := $(wildcard src/*.cpp)
BINS := $(SRCS:src/%.cpp=bin/%)
Now make a rule that depends on all the binaries:
all: $(BINS)
Now make a pattern rule that tells make how to build each one of those binaries:
bin/% : src/%.o
$(CXX) $(CXXFLAGS) -o $# $^ $(LDLIBS)
Now you're actually done, because make already has a built-in rule that knows how to build a .o file into the same directory where the .c file lives, so it can figure out how to build the src/x.o files on its own.
Try something like:
SRC:=${wildcard src/*.cpp}
OBJ:=$(patsubst %.cpp,%.o,${patsubst src/%,bin/%,${SRC}}}
to get the list of the object files, and the rule:
obj/%.o : src/%.cpp
${CXX} -o $# -c $<
for compiling into the right location.
EDIT You have now clarified that each file is a separate main.
SRC:=${wildcard src/*.cpp}
BIN:=$(patsubst %.cpp,,${patsubst src/%,bin/%,${SRC}}}
to get the list of the object files, and the rule:
bin/% : src/%.cpp
${CXX} -o $# $<
will write each output as an executable in bin. To kick it off:
all : ${BIN}
I created the following makefile:
#COMPILER
CC=gcc
CFLAGS=-I./include/ -L. -Wl,-rpath=. -Wall
CORFLAGS=-I./include/ -c -ansi -pedantic-errors -Wall -Wextra -g
COFLAGS=-I./include/ -Wall -Werror -fpic -c
CSOFLAGS=-shared
#vpath
vpath %.h ./include/
vpath %.c ./test/
vpath %.c ./source/
vpath %.o ./obj/
#PATH
SOURCE=./source/
OUT=-o ./obj/$#
TEST=./test/
OBJPATH=./obj/
#LISTS
CFILESWP=$(wildcard ./source/*.c)
TFILESWP=$(wildcard ./test/*.c)
CFILES=$(notdir $(CFILESWP))
TFILES=$(notdir $(TFILESWP))
TOFILES=$(TFILES:.c=.o)
OFILES=$(CFILES:.c=.o)
OFILESWP=$(addprefix ./obj/,$(OFILES))
NAMES=$(TOFILES:_test.o=)
HFILES=$(CFILES:.c=.h)
.PHONY: clean debug release all
debug: CSOFLAGS+=-g
debug: libds.so
release: CSOFLAGS+=-O2
release: libds.so
test: $(NAMES)
all: libds.so $(NAMES)
%: %_test.c libds.so
$(CC) $(CFLAGS) -o $# $< -lds -g
#SHARED LIBRARY
libds.so: $(OFILES)
$(CC) $(CSOFLAGS) -o libds.so $(OFILES)
#OBJFILES
%.o: %.c %.h
$(CC) $(COFLAGS) -o $# $< -g
#CLEAN
clean:
rm -f *.o $(OBJPATH)*.o
rm -f $(NAMES) libds.so
My make file creates a shared library which called libds.so on make command and creates compiled executables on make test command.
it takes source files called TARGET.c from /source/ directory a.k.a stack.c, queue.c, cbuffer.c and compiles them togeher with their test files from /test/ directory aka stack_test.c, queue_test.c, TARGET_NAME_test.c.
All the .h files are located in the /include/ directory.
and there is also a /obj directory which should contains all the object files which created after running the makefile.
How can I make this makefile better?
How can I move all .o files to /obj directory after each run of make?
Is it possible to create each "project" without the need to compile ALL the targets?
I mean, can I write make, which will create the shared library, and then write create stack and it'll create only executable of stack which compiles /source/stack.c, test/stack_test, include/stack.h and all other associated .h files which appear to be inside the code of the source files.
Can I somehow force the makefile to run and compile only the projects that can be compiled and not to stop the "making", the compilation of the files just because several projets that have syntax errors inside of them or some other errors?
For example:
If I have the following projects: stack.c, queue.c, cbuffer.c
and cbuffer cannot be compiled because something is wrong with its code.
I want to be able to run make and make test and compile the other projects that can be compiled like stack and queue and just show me the compilation error of cbuffer but not to stop the make process.
Thanks.
I am now studying C++. I want a makefile which will compile all of the cpp files in the current directory to separate executables. For example:
In a directory there are 3 c++ files, such as examp1.cpp, examp2.cpp and examp3.cpp. I want a makefile which will compile and link them and give examp1.exe, examp2.exe and examp3.exe
I have created a bash script to compile all of them and create exes but I think; that's not the exact way to do this.
I have a a Makefile for ".c", but that does not seem to work here. It is only creating object files and not actually linking it. It is as follows:
SRCS=$(wildcard *.c)
OBJS=(SRCS:.c=.o)
all: $(OBJS)
The above code compiles all the new and modified ".c" files to ".o" files with same name in the current directory.
The bash script I am using to create executables is as follows:
for i in ./*.cpp
do
g++ -Wno-deprecated $i -o `basename $i .cpp`".exe"
done
This means I want whatever ".cpp" files I put in that directory, by using a simple "make all" or anything like that it should compile.
A minimal Makefile that does what you want would be:
#Tell make to make one .out file for each .cpp file found in the current directory
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
#Rule how to create arbitary .out files.
#First state what is needed for them e.g. additional headers, .cpp files in an include folder...
#Then the command to create the .out file, probably you want to add further options to the g++ call.
%.out: %.cpp Makefile
g++ $< -o $# -std=c++0x
You'll have to replace g++ by the compiler you're using and possibly adjust some platform specific setting, but the Makefile itself should work.
This is the Makefile that I use
CC = gcc
CFLAGS = -g -O2 -std=gnu99 -static -Wall -Wextra -Isrc -rdynamic -fomit-frame-pointer
all: $(patsubst %.c, %.out, $(wildcard *.c))
%.out: %.c Makefile
$(CC) $(CFLAGS) $< -o $# -lm
clean:
rm *.out
You should paste it somewhere in your home and whenever you change the dirctory just copy it there. I use an alias in my ~/.basrc to copy it
alias get_makefile_here='cp ~/Makefile ./'
Simply press make and bam, you're done. Also notice the fact that once you're done with the old files it will not rebuild their executable.
My answer builds on top of the answer by #Haatschii
I don't prefer to have the .out prefix to my binaries. Also I used his existing Make syntax to perform clean as well.
CXX=clang++
CXXFLAGS=-Wall -Werror -std=c++11
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
%.out: %.cpp Makefile
$(CXX) $(CXXFLAGS) $< -o $(#:.out=)
clean: $(patsubst %.cpp, %.clean, $(wildcard *.cpp))
%.clean:
rm -f $(#:.clean=)
The simplest makefile you can create that might work for you is this:
all: examp1.exe examp2.exe examp3.exe
That will use make's default rules to create your three programs.
I have a makefile as follows:
CC = gcc
CFLAGS = -fmessage-length=0 -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" $(INCLUDES)
ifdef DEBUG
CFLAGS += -g3
endif
INCLUDES = \
-I../config.include \
-I../log.include \
-I../services.include
SRC_DIR = src
BIN_DIR = bin
BINARY = report
SRCS = $(shell ls $(SRC_DIR)/*.cpp)
OBJS = $(SRCS:%.cpp=%.o)
all: $(OBJS)
#mkdir -p $(BIN_DIR)
$(CC) $(OBJS) -o $(BIN_DIR)/$(BINARY)
clean:
rm -rf $(BIN_DIR) $(OBJS)
However, when I run make, I get the error:
g++ -c -o src/report.o src/report.cpp
src/report.cpp:40:20: error: log.h: No such file or directory
src/report.cpp:41:28: error: services.h: No such file or directory
src/report.cpp:41:28: error: config.h: No such file or directory
I know for a fact that the header files are there, and that they are included correctly. The paths are also correct. There is something wrong with the makefile, but I cannot figure out what.
Notice that even though I set CC = gcc, the output is always g++. This is not a typo, it is actually the output I am getting - again, not sure why.
Help!
You have to redefine CXXFLAGS and CXX and not CFLAGS and CC for .cpp files.
Check the output of make -p and search for %.o: %.cpp rule.
You have no target for the individual object files ($(OBJS)), so Make searches its list of implicit rules, one of which is to make .o files from .cpp files using the C++ compiler, which is set by CXX (which by default is probably g++).