I am trying to compile a C++ program using make. I want it to read the source files from the src folder. Place the object files in the build folder, and put the exe in the bin folder.
I get the following error
/bin/wavfiletool.exe -g -O2 process_begin: CreateProcess(NULL,
/bin/wavfiletool.exe -g -O2, ...) failed. make (e=2): The system
cannot find the file specified.
UPDATE: The problem was I put g++ in for my compiler var instead of &(CC)...woops.
But now it says g++: fatal error: no input files
I am running make using a batch file that sets the environment variables.
SET PATH=C:\Make\GnuWin32\bin;C:\MinGW\bin
make %1
My makefile is as follows.
CC := g++
CFLAGS := -g -O2
BIN_DIR := /bin
BUILD_DIR := /build
SRC_DIR := /src
TARGET := wavfiletool.exe
SOURCES := $(wildcard $(SRC_DIR)/*.c)
OBJECTS := $(SOURCES:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
$(BIN_DIR)/$(TARGET): $(OBJECTS)
$(G++) $# $(CFLAGS) $(OBJECTS)
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
#$(CC) $(CFLAGS) -c $< -o $#
You haven't set the $(G++) variable anywhere so the recipe line for the $(BIN_DIR)/$(TARGET) target is trying to run $# instead of the compiler.
Also you are missing -o on that compilation line so were $(G++) set to g++ correctly you would end up running:
g++ /bin/wavfiletool.exe -g -O2 $(OBJECTS)
which likely isn't what you want.
That being said you probably don't want to be writing directly into /bin either. Did you mean ./bin for a bin directory in the local directory?
Related
I created the following makefile:
#COMPILER
CC=gcc
CFLAGS=-I./include/ -L. -Wl,-rpath=. -Wall
CORFLAGS=-I./include/ -c -ansi -pedantic-errors -Wall -Wextra -g
COFLAGS=-I./include/ -Wall -Werror -fpic -c
CSOFLAGS=-shared
#vpath
vpath %.h ./include/
vpath %.c ./test/
vpath %.c ./source/
vpath %.o ./obj/
#PATH
SOURCE=./source/
OUT=-o ./obj/$#
TEST=./test/
OBJPATH=./obj/
#LISTS
CFILESWP=$(wildcard ./source/*.c)
TFILESWP=$(wildcard ./test/*.c)
CFILES=$(notdir $(CFILESWP))
TFILES=$(notdir $(TFILESWP))
TOFILES=$(TFILES:.c=.o)
OFILES=$(CFILES:.c=.o)
OFILESWP=$(addprefix ./obj/,$(OFILES))
NAMES=$(TOFILES:_test.o=)
HFILES=$(CFILES:.c=.h)
.PHONY: clean debug release all
debug: CSOFLAGS+=-g
debug: libds.so
release: CSOFLAGS+=-O2
release: libds.so
test: $(NAMES)
all: libds.so $(NAMES)
%: %_test.c libds.so
$(CC) $(CFLAGS) -o $# $< -lds -g
#SHARED LIBRARY
libds.so: $(OFILES)
$(CC) $(CSOFLAGS) -o libds.so $(OFILES)
#OBJFILES
%.o: %.c %.h
$(CC) $(COFLAGS) -o $# $< -g
#CLEAN
clean:
rm -f *.o $(OBJPATH)*.o
rm -f $(NAMES) libds.so
My make file creates a shared library which called libds.so on make command and creates compiled executables on make test command.
it takes source files called TARGET.c from /source/ directory a.k.a stack.c, queue.c, cbuffer.c and compiles them togeher with their test files from /test/ directory aka stack_test.c, queue_test.c, TARGET_NAME_test.c.
All the .h files are located in the /include/ directory.
and there is also a /obj directory which should contains all the object files which created after running the makefile.
How can I make this makefile better?
How can I move all .o files to /obj directory after each run of make?
Is it possible to create each "project" without the need to compile ALL the targets?
I mean, can I write make, which will create the shared library, and then write create stack and it'll create only executable of stack which compiles /source/stack.c, test/stack_test, include/stack.h and all other associated .h files which appear to be inside the code of the source files.
Can I somehow force the makefile to run and compile only the projects that can be compiled and not to stop the "making", the compilation of the files just because several projets that have syntax errors inside of them or some other errors?
For example:
If I have the following projects: stack.c, queue.c, cbuffer.c
and cbuffer cannot be compiled because something is wrong with its code.
I want to be able to run make and make test and compile the other projects that can be compiled like stack and queue and just show me the compilation error of cbuffer but not to stop the make process.
Thanks.
I'm trying to write a makefile that contains some bash commands in order to collect the names of the cpp files from a folder.
SRC_FILES=""
CC = g++
CFLAGS = -g
gather-files:
for var in $$(cd ./src && (ls -all *.cpp | awk '{print $$9}')); \
do \
SRC_FILES+="./src/"+"$(var) "; \
done; \
game: gather-files
$(CC) -c $(CFLAGS) $(SRC_FILES)
The SRC_FILES and var variables seems not to update when I run the make game command.
What am I missing?
Ignore the relatively incomplete g++ command, I just want to know how to make the SRC_FILES variable contain all of the names of the cpp files in the src folder.
This is the output of make game:
g++ -c -g ""
clang: error: no input files
LATER EDIT:
Solution, as suggested:
SRC_FILES := $(wildcard src/*.cpp)
CC = g++
CFLAGS = -g
game: $(SRC_FILES)
$(CC) -c $(CFLAGS) $(SRC_FILES)
You are mixing shell commands with makefile commands. That's not valid. The entire recipe is sent to the shell to be run there. Once the recipe has been expanded (which happens once before the shell is invoked) the results cannot contain any make operations.
In short, it's not possible (technically it can be done but it's A Very Bad Idea (tm) so don't) to change make variables from within a shell recipe.
Why don't you use GNU make operations instead?
SRC_FILES := $(wildcard src/*.cpp)
game: $(SRC_FILES)
...
Of course, this is kind of a silly makefile because it will recompile ALL the source files if ANY source file changes. You could get equivalent behavior by just writing a script that ran the compiler.
Your 'Last Edit' is still not ideal, as it builds everthing every time. Try something like this:
SRC_FILES := $(wildcard src/*.cpp)
OBJ_FILES := $(SRC_FILES:.cpp=.o)
DEP_FILES := $(SRC_FILES:.cpp=.d)
#Important: this is =, not :=
DEP_FLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.d
game: $(OBJ_FILES)
$(CC) -o $# $(OBJ_FILES)
# Pattern rule to build .o files
$(OBJ_FILES): %.o : %.cpp %.d
$(CC) $(DEP_FLAGS) -c $(CFLAGS) $< -o $#
#dummy rule to prevent building .d files explicitly.
$(DEP_FILES):
include $(wildcard $(DEP_FILES))
As to what this does -- it first populates SRC_FILES with any cpp files it finds. It then generates a list of object and dependency files from that list. Then we do some magic dependency stuff, which is described here -- basically, when you compile a file, it generates a .d file with a list of all headers it depends on, so now, if anything changes, make knows to rebuild the .c file.
Then there's a static pattern rule to build all the .o files, and a rule to link them all together to the game. Last, but not least, it includes the DEP_FILES that happen to exist when you start make.
I am trying to write a makefile for a C++ project, divided into directories:
makefile
src – (all the .cpp files)
include (all the .h files)
obj (all the .o files)
bin (create the executable there)
I've read a lot about the subject but either it is too simple and they list the files manually or it is too complicated and I am lost.
I tried to write the makefile in many different ways and this is the last one:
CC = g++
CFLAGS = -std=c++11 -c -g -Wall
TARGET = bin/evolveIt
LINKER = g++ -o
# linking flags here
LFLAGS = -Wall -I. -lm
# change these to set the proper directories where each files shoould be
SRCDIR = src
OBJDIR = obj
HDIR = include
BINDIR = bin
SOURCES := $(wildcard $(SRCDIR)/*.cpp)
INCLUDES := $(wildcard $(HDIR)/*.h)
OBJECTS := $(SOURCES:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
rm = rm -f
$(BINDIR)/$(TARGET): $(OBJECTS)
#$(LINKER) $# $(LFLAGS) $(OBJECTS)
#echo "Linking complete!"
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#$(CC) $(CFLAGS) -c $< -o $#
#echo "Compiled "$<" successfully!"
.PHONEY: clean
clean:
But now I have this error:
src/PopulationManager.cpp:4:31: fatal error: PopulationManager.h: No such file or directory
#include "PopulationManager.h"
^
compilation terminated.
Makefile:28: recipe for target 'obj/PopulationManager.o' failed
make: *** [obj/PopulationManager.o] Error 1
I know that I have to use -I when the headers are in a different directory, but it is already in the CFLAGS and LFLAGS and it doesn't change anything if I put it directly in INCLUDES like this:
INCLUDES := -I $(wildcard $(HDIR)/*.h)
There is no error in the program itself, it compiled fine before I put into different directories. The point of this makefile was to avoid writing relative paths in my source files like
include "include/PopulationManager.h"
Any idea of what's wrong with this makefile?
I am now studying C++. I want a makefile which will compile all of the cpp files in the current directory to separate executables. For example:
In a directory there are 3 c++ files, such as examp1.cpp, examp2.cpp and examp3.cpp. I want a makefile which will compile and link them and give examp1.exe, examp2.exe and examp3.exe
I have created a bash script to compile all of them and create exes but I think; that's not the exact way to do this.
I have a a Makefile for ".c", but that does not seem to work here. It is only creating object files and not actually linking it. It is as follows:
SRCS=$(wildcard *.c)
OBJS=(SRCS:.c=.o)
all: $(OBJS)
The above code compiles all the new and modified ".c" files to ".o" files with same name in the current directory.
The bash script I am using to create executables is as follows:
for i in ./*.cpp
do
g++ -Wno-deprecated $i -o `basename $i .cpp`".exe"
done
This means I want whatever ".cpp" files I put in that directory, by using a simple "make all" or anything like that it should compile.
A minimal Makefile that does what you want would be:
#Tell make to make one .out file for each .cpp file found in the current directory
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
#Rule how to create arbitary .out files.
#First state what is needed for them e.g. additional headers, .cpp files in an include folder...
#Then the command to create the .out file, probably you want to add further options to the g++ call.
%.out: %.cpp Makefile
g++ $< -o $# -std=c++0x
You'll have to replace g++ by the compiler you're using and possibly adjust some platform specific setting, but the Makefile itself should work.
This is the Makefile that I use
CC = gcc
CFLAGS = -g -O2 -std=gnu99 -static -Wall -Wextra -Isrc -rdynamic -fomit-frame-pointer
all: $(patsubst %.c, %.out, $(wildcard *.c))
%.out: %.c Makefile
$(CC) $(CFLAGS) $< -o $# -lm
clean:
rm *.out
You should paste it somewhere in your home and whenever you change the dirctory just copy it there. I use an alias in my ~/.basrc to copy it
alias get_makefile_here='cp ~/Makefile ./'
Simply press make and bam, you're done. Also notice the fact that once you're done with the old files it will not rebuild their executable.
My answer builds on top of the answer by #Haatschii
I don't prefer to have the .out prefix to my binaries. Also I used his existing Make syntax to perform clean as well.
CXX=clang++
CXXFLAGS=-Wall -Werror -std=c++11
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
%.out: %.cpp Makefile
$(CXX) $(CXXFLAGS) $< -o $(#:.out=)
clean: $(patsubst %.cpp, %.clean, $(wildcard *.cpp))
%.clean:
rm -f $(#:.clean=)
The simplest makefile you can create that might work for you is this:
all: examp1.exe examp2.exe examp3.exe
That will use make's default rules to create your three programs.
I have a makefile as follows:
CC = gcc
CFLAGS = -fmessage-length=0 -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" $(INCLUDES)
ifdef DEBUG
CFLAGS += -g3
endif
INCLUDES = \
-I../config.include \
-I../log.include \
-I../services.include
SRC_DIR = src
BIN_DIR = bin
BINARY = report
SRCS = $(shell ls $(SRC_DIR)/*.cpp)
OBJS = $(SRCS:%.cpp=%.o)
all: $(OBJS)
#mkdir -p $(BIN_DIR)
$(CC) $(OBJS) -o $(BIN_DIR)/$(BINARY)
clean:
rm -rf $(BIN_DIR) $(OBJS)
However, when I run make, I get the error:
g++ -c -o src/report.o src/report.cpp
src/report.cpp:40:20: error: log.h: No such file or directory
src/report.cpp:41:28: error: services.h: No such file or directory
src/report.cpp:41:28: error: config.h: No such file or directory
I know for a fact that the header files are there, and that they are included correctly. The paths are also correct. There is something wrong with the makefile, but I cannot figure out what.
Notice that even though I set CC = gcc, the output is always g++. This is not a typo, it is actually the output I am getting - again, not sure why.
Help!
You have to redefine CXXFLAGS and CXX and not CFLAGS and CC for .cpp files.
Check the output of make -p and search for %.o: %.cpp rule.
You have no target for the individual object files ($(OBJS)), so Make searches its list of implicit rules, one of which is to make .o files from .cpp files using the C++ compiler, which is set by CXX (which by default is probably g++).