I have a makefile as follows:
CC = gcc
CFLAGS = -fmessage-length=0 -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" $(INCLUDES)
ifdef DEBUG
CFLAGS += -g3
endif
INCLUDES = \
-I../config.include \
-I../log.include \
-I../services.include
SRC_DIR = src
BIN_DIR = bin
BINARY = report
SRCS = $(shell ls $(SRC_DIR)/*.cpp)
OBJS = $(SRCS:%.cpp=%.o)
all: $(OBJS)
#mkdir -p $(BIN_DIR)
$(CC) $(OBJS) -o $(BIN_DIR)/$(BINARY)
clean:
rm -rf $(BIN_DIR) $(OBJS)
However, when I run make, I get the error:
g++ -c -o src/report.o src/report.cpp
src/report.cpp:40:20: error: log.h: No such file or directory
src/report.cpp:41:28: error: services.h: No such file or directory
src/report.cpp:41:28: error: config.h: No such file or directory
I know for a fact that the header files are there, and that they are included correctly. The paths are also correct. There is something wrong with the makefile, but I cannot figure out what.
Notice that even though I set CC = gcc, the output is always g++. This is not a typo, it is actually the output I am getting - again, not sure why.
Help!
You have to redefine CXXFLAGS and CXX and not CFLAGS and CC for .cpp files.
Check the output of make -p and search for %.o: %.cpp rule.
You have no target for the individual object files ($(OBJS)), so Make searches its list of implicit rules, one of which is to make .o files from .cpp files using the C++ compiler, which is set by CXX (which by default is probably g++).
Related
I have a makefile that I need to modify to include the path to libraries.I am trying to run program given to me by someone else. I'm really confused on how the makefile works and don't understand what the previous lines are.
These are the directions given to me to modify the makefile:
Change the lines:
INCS = -I"../../LIB/libpca/include"
LIBS = -L"../../LIB/libpca/build" -lpca -larmadillo
in the Makefile to represent the folder where you installed the libpca and armadillo libraries.
Now I now what my new paths are:
Desktop/PCA-CD/Libraries
but I don't understand what is is that I really need to change.
Here is what the makefile looks like:
PROG = CD
UNAME := $(shell uname)
ifeq ($(UNAME), Darwin)
CXX = clang++ -stdlib=libc++
else
CXX = g++
endif
FLAGS = -O0 -g3 -Wall -std=c++0x -pthread
INCS = -I"../../LIB/libpca/include"
LIBS = -L"../../LIB/libpca/build" -lpca -larmadillo
SRCS = CD.cpp
RM = rm -f
all :
$(CXX) $(FLAGS) $(INCS) $(SRCS) $(LIBS) -o $(PROG)
# $(CXX) $(FLAGS) $(SRCS) -o $(PROG)
clean :
$(RM) $(PROG)
Thanks for any help provided.
I think they're suggesting to change the line:
INCS = -I"../../LIB/libpca/include"
LIBS = -L"../../LIB/libpca/build" -lpca -larmadillo
to
INCS = -I"Desktop/PCA-CD/Libraries/include"
LIBS = -L"Desktop/PCA-CD/Libraries/build" -lpca -larmadillo
Notice that Desktop/PCA-CD/Libraries is a relative path, and assumes that the library is stored in the subdirectory of the build directory. From your build directory, try running ls Desktop/PCA-CD/Libraries/build, to confirm it is right path. If it's not, replace it with the absolute path of the directory where you installed the library.
I have the makefile given below. When I do make I get the following error
cc -c -o timing.o timing.c
test_c.c:5:17: fatal error: test.h: No such file or directory
#include "test.h"
I have manually verfied that test.h is present in ../include path. I am not sure why this is not finding the header file.It would be great if someone could help.Also I would expect g++ instead of cc
# Makefile template for shared library
CXX = g++ # C++ compiler
CXXFLAGS = -fPIC -Wall -Wextra -O2 -g -I../include #CXX flags
LDFLAGS = -lboost_system -shared # linking flags
RM = rm -f # rm command
TARGET_LIB = libtest.a # target lib
C_SRCS := test_a.c test_b.c
CPP_SRCS := test_c.cpp test_d.cpp
OBJS := $(C_SRCS:.c=.o) $(CPP_SRCS:.cpp=.o)
.PHONY: all
all: ${TARGET_LIB}
$(TARGET_LIB): $(OBJS)
$(CXX) $(CXXFLAGS) ${LDFLAGS} -o $# $^
.PHONY: clean
clean:
-${RM} ${TARGET_LIB} ${OBJS}
~
You have not written a rule for building timing.o from timing.c, so Make uses the default rule it has for that.
But that rule uses CFLAGS, not CXXFLAGS. The CXXFLAGS variable appears in the rule for building object files from C++ sources.
So modify CFLAGS instead of CXXFLAGS, and it should work.
I am trying to write a makefile for a C++ project, divided into directories:
makefile
src – (all the .cpp files)
include (all the .h files)
obj (all the .o files)
bin (create the executable there)
I've read a lot about the subject but either it is too simple and they list the files manually or it is too complicated and I am lost.
I tried to write the makefile in many different ways and this is the last one:
CC = g++
CFLAGS = -std=c++11 -c -g -Wall
TARGET = bin/evolveIt
LINKER = g++ -o
# linking flags here
LFLAGS = -Wall -I. -lm
# change these to set the proper directories where each files shoould be
SRCDIR = src
OBJDIR = obj
HDIR = include
BINDIR = bin
SOURCES := $(wildcard $(SRCDIR)/*.cpp)
INCLUDES := $(wildcard $(HDIR)/*.h)
OBJECTS := $(SOURCES:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
rm = rm -f
$(BINDIR)/$(TARGET): $(OBJECTS)
#$(LINKER) $# $(LFLAGS) $(OBJECTS)
#echo "Linking complete!"
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#$(CC) $(CFLAGS) -c $< -o $#
#echo "Compiled "$<" successfully!"
.PHONEY: clean
clean:
But now I have this error:
src/PopulationManager.cpp:4:31: fatal error: PopulationManager.h: No such file or directory
#include "PopulationManager.h"
^
compilation terminated.
Makefile:28: recipe for target 'obj/PopulationManager.o' failed
make: *** [obj/PopulationManager.o] Error 1
I know that I have to use -I when the headers are in a different directory, but it is already in the CFLAGS and LFLAGS and it doesn't change anything if I put it directly in INCLUDES like this:
INCLUDES := -I $(wildcard $(HDIR)/*.h)
There is no error in the program itself, it compiled fine before I put into different directories. The point of this makefile was to avoid writing relative paths in my source files like
include "include/PopulationManager.h"
Any idea of what's wrong with this makefile?
I am new in make file.
I have a program made of
main.cpp
types.hpp
application/coordinator.hpp
application/correlation.hpp
application/handler.hpp
application/settings.hpp
libraries/basket.hpp
libraries/config.hpp
libraries/graphics.hpp
...
I have so many files and the list of my files will be updated so many times. I want the make file recognizes automatically which .o file to be generated or updated. I don't want to update my make file each time I create and include a new file. The output must be generated in a directory called bin
main.cpp is my only cpp file and the rest of my files are hpp.
Till now, this link has inspired me to write this code:
CC=g++
CFLAGS= -g -Wfatal-errors
CFLAGS+= -std=c++11
LIBS= -lboost_filesystem -lboost_system
all: run
run: $(OBJS)
$(CC) $(CFLAGS) $^ main.cpp -o $#
$(OBJS): bin/%.o : bin/%.hpp
How to improve it to working code and what I want?
If you intend to only ever have one cpp file, you could write the makefile in the following way:
CXX := g++
CXXFLAGS := -g -Wall -pedantic -Wextra
HEADERS := types.hpp $(wildcard application/*.hpp) $(wildcard libraries/*.hpp)
all: run
run: main.cpp $(HEADERS)
$(CXX) $(CXXFLAGS) $< -o $#
$(wildcard) will find all headers in application and libraries. The executable will depend on all the headers and main.cpp so if any of them changes, the binary will be rebuilt.
$< means "first dependency". This way, only the cpp file is passed to the compiler.
Note: in GNU make conventions, CC and CFLAGS refer to the C compiler. For C++, the variables are named CXX and CXXFLAGS.
Here's a different scheme: generate the dependency information while you build the software. This works with multiple cpp files creating multiple object files.
CXX := g++
#CPPFLAGS := preprocessor flags, e.g. -I and -D
CXXFLAGS := -g -Wall -pedantic -Wextra -Wfatal-errors -std=c++11 -MD -MP
SOURCES := main.cpp
OBJECTS := $(SOURCES:.cpp=.o)
DEPFILES:= $(OBJECTS:.o=.d)
all: run
# Link the executable
run: $(OBJECTS)
$(CXX) $(LDFLAGS) $^ -o $# $(LIBS)
-include $(DEPFILES)
When .o files are built, the -MD -MP flags tell the compiler to generate the dependency file as a side-effect. These dependency files are included into the makefile if they are present.
This uses GNU make's built-in %.o : %.cpp rule. We just supply parameters to it (CXX, CPPFLAGS, CXXFLAGS).
Make already knows to rebuild .o files if the corresponding .cpp file is newer (either GNU make's built-in rule or a hand-written one). With .d files included into the makefile, we tell make that the object file also depends on the header files and should be rebuilt when one of them changes. But the rule to rebuild the .o is always %.o : %.cpp
I have this makefile below. While it compiles properly at the moment, I'm running into a really weird and tedious issue where I have to run make twice to compile the code.
The first time I call make, I get this error:
./src/gravity.cpp:1:31: fatal error: gravity.h: No such file or directory
compilation terminated.
I have a lot more source files added under OBJECTS = .., and that message repeats for each one of them. Of course, this would indicate that I didn't link the headers correctly, except that when I run make again, everything compiles smoothly.
An interesting observation may be that main.cpp doesn't complain about a missing gravity.h, but I'm not sure how it relates.
I have header guards on all my header files. If it helps, this is for a C++ SDL/OpenGL application.
My makefile is below. Thanks!
OUTPUT_NAME = output_file
INC_DIR = ./inc
SRC_DIR = ./src
BIN_DIR = ./bin
INCLUDES= \
-I${SRC_DIR}
SRC := $(shell find $(SRC_DIR) -name '*.cpp')
INC := $(shell find $(INC_DIR) -name '*.h')
CXX = g++
CXXFLAGS = -g -Wall -std=c++0x -I${INC_DIR} -I./lib/glm
LIBFLAGS = -lSDL -lGL -lGLU -lglut
OBJECTS = \
${BIN_DIR}/main.o \
${BIN_DIR}/gravity.o
DEPS = $(BIN_DIR)/${OUTPUT_NAME}.deps
all: ${DEPS} ${OUTPUT_NAME}
${DEPS}: ${INC} ${SRC}
#${CXX} -M ${SRC} > ${DEPS}
${OUTPUT_NAME}: ${OBJECTS}
${CXX} ${CXXFLAGS} ${OBJECTS} -o ${OUTPUT_NAME} ${LIBFLAGS}
${OBJECTS}: ${BIN_DIR}/%.o : ${SRC_DIR}/%.cpp
${CXX} ${CXXFLAGS} $< -c -o $#
force:
$(MAKE) fullclean
$(MAKE)
clean:
rm ${OBJECTS} ${OUTPUT_NAME}
fullclean:
rm ${OBJECTS} ${DEPS} ${OUTPUT_NAME}
run:
clear
./${OUTPUT_NAME}
style:
astyle --style=java --indent=spaces=4 ${SRC} ${INC}
.PHONY: all clean fullclean run style force
include $(DEPS)
The rule to build your .deps file:
${DEPS}: ${INC} ${SRC}
#${CXX} -M ${SRC} > ${DEPS}
will unconditionally create the ${DEPS} file even if the invocation of the C++ compiler fails. (It probably would have been better to have used -o.)
It is also missing the -I options which would allow it to find the header files.
As a result of the second error, it will fail when run. As a result of the first error, it will nevertheless create a .deps file. The second time you invoke make, it will not trigger the ${DEPS} rule because the .deps file is newer than any dependency.
Also, I don't understand
INCLUDES= \
-I${SRC_DIR}
It's not correct (I think: it should be INC_DIR, and it's missing ./lib/glm), and you don't use it anywhere.