I have been supplied with the following makefile:
CXX=g++
CXXFLAGS=-std=c++11 -g -O2
LDFLAGS=-ltbb
EXE=$(basename $(wildcard *.cc))
all: $(EXE)
clean:
rm -fr $(EXE) *.dSYM
I am new to makefiles and In order to get it working in Ubuntu, I need to modify it such that the LDFLAGS comes after the source file in the compile command. How can I do this? My attempt is as follows:
CXX=g++
CXXFLAGS=-std=c++11 -g -O2
LDFLAGS=-ltbb
SRCS=$(wildcard *.cc)
EXES=$(subst .cc,,$(SRCS))
all: $(EXES)
$(CXX) $(CXXFLAGS) $(SRCS) $(LDFLAGS) -o $(EXES)
clean:
rm -fr $(EXE) *.dSYM
Libraries should be added to LDLIBS instead of LDFLAGS. Try this in your original makefile:
LDLIBS=-ltbb
See here for reference.
Related
I have a Makefile which is minimal, yet complete. It is the following:
OUT = example
INSTALL_DIR = /usr/local/bin
OBJECT = ./obj
SOURCE = ./src
SRC := $(shell find $(SOURCE) -name *.cc)
OBJ := $(SRC:%=$(OBJECT)/%.o)
DEPS := $(OBJ:.o=.d)
INC_DIRS := $(shell find $(SOURCE) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS))
CC = gcc
CFLAGS = -pipe -fmodules-ts -std=c++2a
DEBUG_FLAGS := $(CFLAGS) -g -Wall -Wextra
RELEASE_FLAGS := $(CFLAGS) -O3 -flto
debug: $(OBJ)
#echo "Building the DEBUG binary..."
#$(CC) $(OBJ) -o $(OUT) $(DEBUG_FLAGS)
#echo "The binary was built successfully!"
release: $(OBJ)
#echo "Building the RELEASE binary..."
#$(CC) $(OBJ) -o $(OUT) $(RELEASE_FLAGS)
#echo "The binary was built successfully!"
install: $(OUT)
#cp $(OUT) $(INSTALL_DIR)
uninstall:
#rm $(INSTALL_DIR)/$(OUT)
$(OBJECT)/%.cc.o: %.cc
#mkdir -p $(dir $#)
#echo "Building $#..."
#$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -rf $(OBJECT) $(OUT)
-include $(DEPS)
There is a directory called "src" which includes the source files. When I'm running make, I will get a compilation error about having to first create modules before using them. If I do create them manually, then I will be able to use "Make" and it will work then it will work. Is there a way to automatically create them?
I recommend using g++-11 instead of just gcc, since versions <=10 do not really include module support asides from the deprecated TS. Then also, use flag -std=c++20.
Also, I have (painful) experience using dependency files with gcc, since that particular feature is not really fully implemented. Last I checked (beginning of nov '21) the dependency files don't actually do anything as pertains to modules.
That being said, what you write should work. And it would, if the compiler-support for modules was finished.
I'm actually experiencing some issues while linking an OpenGL/freeglut shared library (.so) with a C++ project. I'm sure that the problem is in my Makefile since the code I use to load (using the dlopen/dlsym/dlclose functions) works fine with other shared libraries.
I thought it comes from headers inclusions but the OpenGL project I'm trying to work with compiles when I create an executable of it. I've also checked the glut FAQ but the solution now redirect to a dead link So there is my Makefile content, does anyone see where I am wrong ?
TARGET = lib_opengl.so
CC = g++
SRC = GL_Handler.cpp \
GL_Utils.cpp
DEVIL_CFLAGS := $(shell pkg-config --cflags IL)
DEVIL_LIBS := $(shell pkg-config --libs IL)
LIBS += -lGL -lGLU -lglut $(DEVIL_CFLAGS) $(DEVIL_LIBS)
CFLAGS = -W -Werror -Wall -ansi -pedantic -fPIC -shared -L/usr/X11R6/lib/ $(LIBS)
SRCDIR = src
OBJDIR = obj
SOURCES := $(addprefix src/, $(SRC))
OBJECTS := $(SOURCES:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
rm = rm -rf
mkdir = mkdir -p
$(TARGET): $(OBJECTS)
#$(CC) $(CFLAGS) -o $# $(OBJECTS)
#echo $(TARGET)" compiled !"
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#$(mkdir) $(OBJDIR)
#$(CC) $(CFLAGS) -c $< -o $#
all : $(TARGET)
clean :
#$(rm) $(OBJDIR)
#echo "Binary files deleted"
fclean : clean
#$(rm) $(TARGET) $(LINK)
#echo "Binary and executable files are deleted"
re : fclean all
.PHONY: all clean fclean re
And there is the result when I'm trying to link it with my shared libraries loader.
./so_loader ./lib/lib_opengl.so
./so_loader: symbol lookup error: ./lib/lib_opengl.so: undefined symbol: glutInit
I hope that my problem is understandable and thanks for reading.
As a start, use variable LDFLAGS for linking instead of CFLAGS which is meant for compilation. Something like this:
LDFLAGS = -L/usr/X11R6/lib
...
$(TARGET): LDFLAGS += -shared -Wl,--no-undefined
$(TARGET): $(OBJECTS)
#$(CC) $(LDFLAGS) -o $# $(OBJECTS) ${LIBS}
I Just started fooling around using Google Protocol Buffers and I am trying to incorporate the C++ output files from the protocol buffer compiler into my project. I have Been using a simple makefile for my projects so far and it does the trick for building source files all sharing the same extension. I use ".cpp" for my source files but Google Protocol Buffers outputs its source as ".pb.cc" files. I need to be able to compile and link both types of source files into one executable.
I have been searching and fiddling around with my makefile for a few hours now and have had no success.
My Current Makefile:
PROGRAM_NAME=aserv
CC=gcc
CXX=g++
RM=rm -f
CPPFLAGS=-g --std=c++14 -O3 -I/usr/local/include/
LDFLAGS=-g -L/usr/local/lib -L/usr/local/lib/boost
LDLIBS= -lrtaudio -pthread -lboost_system -lprotobuf
INSTALL_DIR = /usr/local/bin/
SRCS=$(wildcard *.cpp)
OBJS=$(subst .cpp,.o,$(SRCS))
all: $(PROGRAM_NAME)
$(PROGRAM_NAME): $(OBJS)
$(CXX) $(LDFLAGS) -o $(PROGRAM_NAME) $(OBJS) $(LDLIBS)
depend: .depend
.depend: $(SRCS)
rm -f ./.depend
$(CXX) $(CPPFLAGS) -MM $^>>./.depend;
clean:
$(RM) $(OBJS) $(PROGRAM_NAME) .depend
install:
cp $(PROGRAM_NAME) $(INSTALL_DIR)$(PROGRAM_NAME)
uninstall:
$(RM) $(INSTALL_DIR)$(PROGRAM_NAME)
dist-clean: clean
$(RM) *~ .depend
include .depend
I am not too well versed in writing makefiles yet, so I just don't quite know what to do to make this work.
If it helps i have GNU make 4.1 and gcc 5.3.1 on Ubuntu 16.04 beta
I couldnt get your original Makefile to work so I changed a few things but I think the tricky part with this is the implicit rules that make generates to build your .o files. I think for the .pb.cc files you need to generate .pb.o objects so that the implicit rules can match them.
Try this:
PROGRAM_NAME = aserv
CC = gcc
CXX = g++
RM = rm -f
CXXFLAGS = --std=c++14 -pthread -g -O3 -MMD -MP
CPPFLAGS = -I/usr/local/include/
LDFLAGS = -L/usr/local/lib -L/usr/local/lib/boost
LDLIBS = -lrtaudio -lboost_system -lprotobuf
INSTALL_DIR = /usr/local/bin
SRCS = $(wildcard *.cpp) $(wildcard *.pb.cc)
OBJS = $(subst .pb.cc,.pb.o,$(subst .cpp,.o,$(SRCS)))
DEPS = $(subst .pb.cc,.pb.d,$(subst .cpp,.d,$(SRCS)))
all: $(PROGRAM_NAME)
$(PROGRAM_NAME): $(OBJS)
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -o $# $^ $(LDFLAGS) $(LDLIBS)
-include $(DEPS)
clean:
$(RM) $(OBJS) $(PROGRAM_NAME)
install:
cp $(PROGRAM_NAME) $(INSTALL_DIR)
uninstall:
$(RM) $(INSTALL_DIR)/$(PROGRAM_NAME)
dist-clean: clean
$(RM) *~ $(DEPS)
If you wanto to only strictly rely on Make, and not the surrounding shell you can add another set of SRC and OBJ variables, which will serve as a second set of dependencies.
Add these right below the first set:
SRC1=$(wildcard *.pb.cc)
OBJ1=$(subst .pb.cc,.o,$(SRC1))
And change the .depend and $(PROGRAM_NAME) rule:
.depend: $(SRCS) $(SRC1)
$(PROGRAM_NAME): $(OBJS) $(OBJ1)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
%.o: %.c
$(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) -c -o $# $<
So I can compile my code (fftw_ex.c) directly with:
login$ gcc -o -g fftw_ex fftw_ex.c -I$TACC_FFTW3_INC -L$TACC_FFTW3_LIB -lfftw3
However, my professor prefers that we use a Makefile. I am just learning how to use Makefile and make, and I'm having trouble creating the Makefile. So far, this is what I have:
# RULES
EXEC := fftw_ex
SRC := $(wildcard *.c)
OBJ := $(patsubst %.c,%.o,%(SRC))
# OPERATIONS
CC := gcc
CFLAGS := -O3 -I$TACC_FFTW3_INC
LDFLAGS := -L$TACC_FFTW3_LIB
LDLIBS := -lfftw3
$(EXEC): $(OBJ)
$(CC) $(LDFLAGS) $(LDLIBS) -o -g $# $^
%.o: %.c
$(CC) $(CFLAGS) -c $<
# PHONY TARGETS
.PHONY: clean
clean:
#echo Cleaning...;rm -rf *.o fftw_ex
I know there's a problem with the SRC line, as i'm getting the error message:
make: *** No rule to make target `%(SRC)', needed by `fftw_ex'. Stop.
Any help to get this to work would be appreciated.
1)To resolve:
No rule to make target `%(SRC)'
replace %(SRC) in
OBJ := $(patsubst %.c,%.o,%(SRC))
with $(SRC)
2)In line:
$(CC) $(LDFLAGS) $(LDLIBS) -o -g $# $^
you have mistake: -o -g, should be -g -o
Help me with makefile, please. I want `make' to recompile only files that have been changed. Here is my makefile:
ROOT_DIR= ..
BUILD_TYPE= Release
BUILD_DIR= $(ROOT_DIR)/$(BUILD_TYPE)
O_DIR= $(BUILD_DIR)/obj
TARGETS= ftp_auto_backup sftp_auto_backup
CXX= g++
CXXFLAGS= -DBOOST_THREAD_USE_LIB -O3 -Wall -fmessage-length=0
FTP_LDFLAGS= -static-libstdc++ -static-libgcc -s -L $(ROOT_DIR)/lib/Release -l:libboost_thread-mgw46-mt-1_49.a -l:libcommon.a \
-l:libfile.a -l:libfilesearcher.a -l:libftpclient.a -l:libftplib.a -l:libdbclient.a -l:libsqlite3.a -l:libscheduler.a -l:libws2_32.a
SFTP_LDFLAGS= -static-libstdc++ -static-libgcc -s -L $(ROOT_DIR)/lib/Release -l:libboost_thread-mgw46-mt-1_49.a -l:libcommon.a \
-l:libfile.a -l:libfilesearcher.a -l:libdbclient.a -l:libsqlite3.a -l:libscheduler.a -l:libsftpclient.a -l:libws2_32.a -l:libssh.dll
OBJECTS= appconfig.o backuplauncher.o clientbackup.o main.o
LD_OBJECTS= $(addprefix $(O_DIR)/,$(OBJECTS))
all: init $(TARGETS)
debug: CXXFLAGS= -O0 -g3 -Wall -fmessage-length=0
debug: BUILD_TYPE= Debug
debug: all
init:
#mkdir -p $(BUILD_DIR)
#mkdir -p $(O_DIR)
ftp_auto_backup: set_type_ftp $(OBJECTS)
$(CXX) -o $(BUILD_DIR)/$#.exe $(LD_OBJECTS) $(FTP_LDFLAGS)
sftp_auto_backup: set_type_sftp $(OBJECTS)
$(CXX) -o $(BUILD_DIR)/$#.exe $(LD_OBJECTS) $(SFTP_LDFLAGS)
set_type_ftp:
$(eval CXXFLAGS+=-DPROJECT_TYPE=FTP)
set_type_sftp:
$(eval CXXFLAGS+=-DPROJECT_TYPE=SFTP)
%.o: %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $(O_DIR)/$#
clean:
rm -rf $(addprefix $(ROOT_DIR)/Release/obj/,$(OBJECTS)) $(addprefix $(ROOT_DIR)/Debug/obj/,$(OBJECTS))
rm -rf $(addprefix $(ROOT_DIR)/Release/,$(addsuffix .exe,$(TARGETS))) $(addprefix $(ROOT_DIR)/Debug/,$(addsuffix .exe,$(TARGETS)))
Yes, I know about Generating Prerequisites Automatically, but should I really use it?
Thanks in advance!
Your targets depend on objects in the current directory, not in obj/. Change to this:
ftp_auto_backup: set_type_ftp $(LD_OBJECTS)
$(CXX) -o $(BUILD_DIR)/$#.exe $(LD_OBJECTS) $(FTP_LDFLAGS)
sftp_auto_backup: set_type_sftp $(LD_OBJECTS)
$(CXX) -o $(BUILD_DIR)/$#.exe $(LD_OBJECTS) $(SFTP_LDFLAGS)
# (...)
$(O_DIR)/%.o: %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $#
And yes, if you want your object files to recompile not only when you change the .cpp file, but also when you change the header (.h) files, you need to generate those prerequisites...
I suppose that %.o : %.cpp is not enough, you should use VPATH to let know make where the sources are:
vpath %.cpp src