What is the oposite of EXPECT_CALL? - unit-testing

I have some expectations like EXPECT_CALL (...)
EXPECT_CALL(t1, foo()).Times(1);
I want to create the oposite.
I expect that a certain function won't be executed.
What is the method I should use?
Something like EXPECT_NOT_CALL (...) ?

In GTest something similar to EXPECT_NOT_CALL doesn't exist however, there are several options to receive this behaviour:
1.Create a StrictMock. In StrictMock any unexpected called cause a failure.
2.Use .Times(0):
EXPECT_CALL(t1, foo()).Times(0);
In this option you use the count mechanism however, it checks if the value is 0.(so any call leads a failure...)
3.Use method 2 and create a Macro:
#define EXPECT_NOT_CALL(a,b) EXPECT_CALL(a, b).Times(0);

Related

Use Mockito to check that method gets called with different values

im quite familar with Mocktio. But never needed something like this before:
Within my Test i like to verify that a method gets called with several values that represent a kind of "loading started". lets say "loading started" and "loading finished with result T". The order of those state change matters!
So, in pseudo code it would do something like this:
resultObject ...
clientcode.requestDataload()
// Order of below state changes is imporant
verifyThat(resultObject.data).wasCalledWith("loading started")
verifyThat(resultObject.data).wasCalledWith("loading finished with result T")
Thanks for pointing me into some direction.
You can use the verifiy method from Mockito:
verify(mockInstance, times(1)).method(ArgumentMatchers.eq("what you want"))
where method is the method that the call need to be checked, and the ArgumentMatchers are the arguments passed to the method for the call (you can use any() too).
You can use InOrder:
val inOrder = inOrder(yourMock)
inOrder.verify(yourMock).yourMethod("loading started")
inOrder.verify(yourMock).yourMethod("loading finished with result T")

How to get the current spdlog level?

I need to turn off the spdlog level before some code then return it to the previous value after.
How do I get the current level before turning it off?
To get current level of logger use logger::level().
To set new level use logger::set_level().
Scenario 1: User-constructed logger
If you have a spdlog::logger object you're using (say, my_logger), then:
You can obtain the level with: my_logger.level().
If you just want to know whether a certain-level message would be logged, then use my_logger.should_log(some_level) where some_level could be, for example spdlog::level::debug.
Scenario 2: The global logger
Now suppose you're using the global logger (e.g. you emit log messages using spdlog::info(), spdlog::error() and such).
spdlog version 1.8.0 and later
You can obtain the global log level with a call to spdlog::get_level() (which is a freestanding function, not a method).
spdlog versions before 1.8.0
You need to get your hand on the implicit logger object - by callingspdlog::default_logger_raw() (it gets you a pointer.) Now just proceed as in Scenario 1 above.
There seems now to be a function to get the global logging level:
spdlog::get_level();

Test whether a log message is generated using Boost.Log

I am currently using Boost.Log in one of my software projects. There is one case, where I report an error condition by using a log message. I would like to test whether this condition is detected correctly using google testing framework. Just to be clear, I want to test whether the message is generated. It may be removed by a filter, but this should not cause the test to fail. Is this possible at all? Any hints? Thanks!
For base yes-or-no testing, simply use assert, something like this:
#include <assert.h> /* assert */
void print_number(int* myInt) {
assert (myInt!=NULL);
// Boost.Log stuff...
// print_number stuff...
}
this will give you a straight up message (depending on compiler/OS) if the test fails.

Assert statement in Verilog

I'm completely new to Verilog, so bear with me.
I'm wondering if there is an assert statement in Verilog. In my testbench, I want to be able to assert that the outputs of modules are equal to certain values.
For example,
mymodule m(in, out);
assert(out == 1'b1);
Googling gave me a few links, but they were either too complex or didn't seem to be what I wanted.
There is an open source library for assertions called OVL. However, it's pretty heavy. One trick I nicked from there is creating a module to do assertions.
module assert(input clk, input test);
always #(posedge clk)
begin
if (test !== 1)
begin
$display("ASSERTION FAILED in %m");
$finish;
end
end
endmodule
Now, any time you want to check a signal, all you have to do is instantiate an assertion in your module, like this:
module my_cool_module(input clk, ...);
...
assert a0(.clk(clk), .test(some_signal && some_other_signal));
...
endmodule
When the assertion fails, you'll get a message like this:
ASSERTION FAILED in my_cool_module.a0
The %m in the display statement will show the entire hierarchy to the offending assertion, which is handy when you have a lot of these in a larger project.
You may wonder why I check on the edge of the clock. This is subtle, but important. If some_signal and some_other_signal in the expression above were assigned in different always blocks, it's possible the expression could be false for a brief period of time depending on the order that your Verilog simulator schedules the blocks (even though the logic was entirely valid). This would give you a false negative.
The other thing to note above is that I use !==, which will cause the assertion to fail if the test value is X or Z. If it used the normal !=, it could silently give a false positive in some cases.
Putting the above together with a macro works for me:
`define assert(signal, value) \
if (signal !== value) begin \
$display("ASSERTION FAILED in %m: signal != value"); \
$finish; \
end
Then later in my test module:
initial begin // assertions
#32 `assert(q, 16'hF0CB)
end
As an example test fail case:
ASSERTION FAILED in test_shift_register: q != 16'hF0CB
you can write like this
if(!(out==1'b1)) $finish;
If your simulator supports SystemVerilog syntax, there is an assert keyword which does what you want.
Verilog doesn't support assertions. Some tools support PSL, which places the assertions in comments but this is non-standard. You should consider using hierarchical references from a testbench instead otherwise you have to place each assertion in a process which will get messy.
The easiest way to mimic C-like assertions is probably a `define since this will make them global.
`define assert(condition) if(condition) begin $finish(1); end
In order to check signals in a non-procedural context, such as your example, you will need a different macro that builds a condition signal and then triggers a test event for that signal.
`define assert_always(condition) generate if(1) begin wire test = condition; always #(test) `assert(condition) end endgenerate
The generate above will create a new scope for the variable test so multiple instances should work.
A better way in a procedural might be to create a task in a separate file and then include that in any module declaration.
task assert(input condition);
if(!condition)
$finish(2);
endtask
For non-procedural contexts you'll need to create a module containing a process and instance that module. This will require a unique name for each instance unless you put it in a generate block.

Javassist: Generate "assert" statement

I try to add an "assert" statement to a method.
But I get this exception:
Caused by: compile error: assert(boolean) not found in mypackage.MyClassThatIsInstrumented
at javassist.compiler.TypeChecker.atMethodCallCore(TypeChecker.java:716)
at javassist.compiler.TypeChecker.atCallExpr(TypeChecker.java:681)
at javassist.compiler.JvstTypeChecker.atCallExpr(JvstTypeChecker.java:156)
at javassist.compiler.ast.CallExpr.accept(CallExpr.java:45)
at javassist.compiler.CodeGen.doTypeCheck(CodeGen.java:241)
at javassist.compiler.CodeGen.atStmnt(CodeGen.java:329)
at javassist.compiler.ast.Stmnt.accept(Stmnt.java:49)
at javassist.compiler.CodeGen.atStmnt(CodeGen.java:350)
at javassist.compiler.ast.Stmnt.accept(Stmnt.java:49)
at javassist.compiler.CodeGen.atMethodBody(CodeGen.java:291)
at javassist.compiler.Javac.compileBody(Javac.java:222)
at javassist.CtBehavior.setBody(CtBehavior.java:360)
... 30 more
Any ideas how to solve that?
A workaround is to implement the assertion as a conditional:
if(Foo.class.desiredAssertionStatus() && expr) {
throw new AssertionError();
}
This is basically equivalent to
assert expr;
Now it is a matter of how you would like to inject it. If you need to assert against the method parameters, you can use method.insertBefore(); if you're asserting the result, you can use method.insertAfter().
If the statement needs to be inserted into the method's body, somewhere in between the statements, then you can use ExprEditor to match the required statement where you want this new statement to be injected