Incremental build with GCC and manual makefile? - c++

I am coding to the NRF51822 bluetooth chip, in Eclipse with GCC and a makefile that I maintain myself.
My problem is that every time I press build, it will compile everything, which is beginning to take quite some time. I am not that experienced in creating and maintaining make-files, so I have no idea where to start in order to get it to build incremtal instead?
My makefile is composed like this (I know there's a lot, and I haven't created this myself - found it in a tutorial, so I don't know what's relevant and what's not :-) ):
PROJECT_NAME := my_project
export OUTPUT_FILENAME
#MAKEFILE_NAME := $(CURDIR)/$(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))
MAKEFILE_NAME := $(MAKEFILE_LIST)
MAKEFILE_DIR := $(dir $(MAKEFILE_NAME) )
TEMPLATE_PATH = nrf51_sdk/toolchain/gcc
ifeq ($(OS),Windows_NT)
include $(TEMPLATE_PATH)/Makefile.windows
else
include $(TEMPLATE_PATH)/Makefile.posix
endif
MK := mkdir
RM := rm -rf
#echo suspend
ifeq ("$(VERBOSE)","1")
NO_ECHO :=
else
NO_ECHO := #
endif
# Toolchain commands
CC := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-gcc"
AS := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-as"
AR := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ar" -r
LD := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ld"
NM := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-nm"
OBJDUMP := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objdump"
OBJCOPY := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objcopy"
SIZE := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-size"
#function for removing duplicates in a list
remduplicates = $(strip $(if $1,$(firstword $1) $(call remduplicates,$(filter-out $(firstword $1),$1))))
#source common to all targets
C_SOURCE_FILES += \
main.c \
file1.c \
file2.c \
file3.c \
file4.c \
#assembly files common to all targets
ASM_SOURCE_FILES = nrf51_sdk/toolchain/gcc/gcc_startup_nrf51.s
#includes common to all targets
INC_PATHS = -I Dir1/
INC_PATHS = -I Dir2
INC_PATHS += -I Dir3
INC_PATHS += -I Dir4
OBJECT_DIRECTORY = _build
LISTING_DIRECTORY =$(OBJECT_DIRECTORY)
OUTPUT_BINARY_DIRECTORY =$(OBJECT_DIRECTORY)
# Sorting removes duplicates
BUILD_DIRECTORIES := $(sort $(OBJECT_DIRECTORY) $(OUTPUT_BINARY_DIRECTORY) $(LISTING_DIRECTORY) )
#flags common to all targets
CFLAGS = -DSOFTDEVICE_PRESENT
CFLAGS += -DNRF51
CFLAGS += -DS110
CFLAGS += -DBOARD_PCA10028
CFLAGS += -DBLE_STACK_SUPPORT_REQD
CFLAGS += -mcpu=cortex-m0
CFLAGS += -mthumb -mabi=aapcs --std=gnu99
CFLAGS += -Wall -O0 -g3
CFLAGS += -mfloat-abi=soft
# keep every function in separate section. This will allow linker to dump unused functions
CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing
#CFLAGS += -flto -fno-builtin
# keep every function in separate section. This will allow linker to dump unused functions
LDFLAGS += -Xlinker -Map=$(LISTING_DIRECTORY)/$(OUTPUT_FILENAME).map
LDFLAGS += -mthumb -mabi=aapcs -L $(TEMPLATE_PATH) -T$(LINKER_SCRIPT)
LDFLAGS += -mcpu=cortex-m0
# let linker to dump unused sections
LDFLAGS += -Wl,--gc-sections
# use newlib in nano version
LDFLAGS += --specs=nano.specs -lc -lnosys
# Assembler flags
ASMFLAGS += -x assembler-with-cpp
ASMFLAGS += -DSOFTDEVICE_PRESENT
ASMFLAGS += -DNRF51
ASMFLAGS += -DS110
ASMFLAGS += -DBOARD_PCA10028
ASMFLAGS += -DBLE_STACK_SUPPORT_REQD
#default target - first one defined
default: clean nrf51422_xxac_s110
#building all targets
all: clean
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e cleanobj
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e nrf51422_xxac_s110
#target for printing all targets
help:
#echo following targets are available:
#echo nrf51422_xxac_s110
#echo flash_softdevice
C_SOURCE_FILE_NAMES = $(notdir $(C_SOURCE_FILES))
C_PATHS = $(call remduplicates, $(dir $(C_SOURCE_FILES) ) )
C_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILE_NAMES:.c=.o) )
ASM_SOURCE_FILE_NAMES = $(notdir $(ASM_SOURCE_FILES))
ASM_PATHS = $(call remduplicates, $(dir $(ASM_SOURCE_FILES) ))
ASM_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(ASM_SOURCE_FILE_NAMES:.s=.o) )
vpath %.c $(C_PATHS)
vpath %.s $(ASM_PATHS)
OBJECTS = $(C_OBJECTS) $(ASM_OBJECTS)
nrf51422_xxac_s110: OUTPUT_FILENAME := nrf51422_xxac_s110
nrf51422_xxac_s110: LINKER_SCRIPT=ble_app_hrs_gcc_nrf51.ld
nrf51422_xxac_s110: $(BUILD_DIRECTORIES) $(OBJECTS)
#echo Linking target: $(OUTPUT_FILENAME).out
$(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e finalize
## Create build directories
$(BUILD_DIRECTORIES):
echo $(MAKEFILE_NAME)
$(MK) $#
# Create objects from C SRC files
$(OBJECT_DIRECTORY)/%.o: %.c
#echo Compiling file: $(notdir $<)
#echo arm-none-eabi-gcc $(CFLAGS) $(INC_PATHS) -c -o $# $<
$(NO_ECHO)$(CC) $(CFLAGS) $(INC_PATHS) -c -o $# $<
# Assemble files
$(OBJECT_DIRECTORY)/%.o: %.s
#echo Compiling file: $(notdir $<)
$(NO_ECHO)$(CC) $(ASMFLAGS) $(INC_PATHS) -c -o $# $<
# Link
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out: $(BUILD_DIRECTORIES) $(OBJECTS)
#echo Linking target: $(OUTPUT_FILENAME).out
$(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
## Create binary .bin file from the .out file
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin: $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
#echo Preparing: $(OUTPUT_FILENAME).bin
$(NO_ECHO)$(OBJCOPY) -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin
## Create binary .hex file from the .out file
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex: $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
#echo Preparing: $(OUTPUT_FILENAME).hex
$(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex
finalize: genbin genhex echosize
genbin:
#echo Preparing: $(OUTPUT_FILENAME).bin
$(NO_ECHO)$(OBJCOPY) -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin
## Create binary .hex file from the .out file
genhex:
#echo Preparing: $(OUTPUT_FILENAME).hex
$(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex
echosize:
-#echo ""
$(NO_ECHO)$(SIZE) $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
-#echo ""
clean:
$(RM) $(BUILD_DIRECTORIES)
cleanobj:
$(RM) $(BUILD_DIRECTORIES)/*.o
flash: $(MAKECMDGOALS)
#echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$<.hex
nrfjprog --reset --program $(OUTPUT_BINARY_DIRECTORY)/$<.hex)
## Flash softdevice
flash_softdevice:
#echo Flashing: s110_softdevice.hex
nrfjprog --reset --program nrf51_sdk/softdevice/s110/hex/s110_softdevice.hex

all: clean
check this line. The default (first) Target of your Makefile depends on clean, so before any build is started, the clean target is executed that likely will remove all built files, to rebuild them.
Drop the clean and you should get the incremental behaviour make was designed for.

Related

How to output .o files into one specific folder?

I'm currently using MinGW64, G++, and a makefile to compile my c++ project on VSCode. I have two src directories src and src/vendor/imGui containing .cpp files that I compile. As of now, the makefile is able to compile both src folders. However, the .o files are outputted in their respective src folders. How can I make it so that every .o file generated gets sent to one specific folder/directory?
Current Makefile:
CXX = g++
CXXFLAGS := -std=c++17 -Wall -Wextra -g
LFLAGS += -LC:/mingw64/x86_64-w64-mingw32/bin
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SRC += src/vendor/imGui
INCLUDE := include
LIB := lib
ifeq ($(OS),Windows_NT)
MAIN := main.exe
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INCLUDES += -IC:/Users/kimda/Desktop/Projects/C++/OpenGL/src/vendor/imGui
LIBS := $(patsubst %,-L%, $(LIBDIRS:%/=%))
LIBS += -lglew32
LIBS += -lopengl32
LIBS += -lglfw3
LIBS += -lgdi32
LIBS += -lglu32
SOURCES := $(wildcard $(patsubst %,%/*.cpp, $(SOURCEDIRS)))
OBJECTS := $(SOURCES:.cpp=.o)
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all: $(OUTPUT) $(MAIN)
#echo Building complete!
$(OUTPUT):
#$(MD) $(OUTPUT)
$(MAIN): $(OBJECTS)
#$(CXX) $(CXXFLAGS) $(INCLUDES) -o $(OUTPUTMAIN) $(OBJECTS) $(LFLAGS) $(LIBS)
.cpp.o:
#$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $#
.PHONY: clean
clean:
#$(RM) $(OUTPUTMAIN)
#$(RM) $(call FIXPATH,$(OBJECTS))
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run: clean all
#./$(OUTPUTMAIN)
#echo Executing complete!
If I understand you correctly you want to send all object files to some 'build' directory.
I usually do something like this
BUILDDIR := build
[...]
OBJECTS := $(addprefix $(BUILDDIR)/,$(SOURCES:.cpp=.o))
[...]
and then change your
.cpp.o:
#$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $#
to
$(BUILDDIR)/%.o: %.cpp
#$(MD) $(dir $#)
#$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $#

Recursive Makefile to build .o files

I am writing a simple kernel and all is going well so far.
I am using a Makefile to build the system through the shell.
However, I wish to move and reorganise the file structure but, my the makefile uses absolute linking.
How can I refactor this to compile all .cpp/.c files and .s files to an out folder and link them, without needing to define each folder path?
CC = ~/opt/cross/bin/i386-elf-g++
AS = ~/opt/cross/bin/i386-elf-as
LNFLAGS = -T linker.ld -melf_i386
CCFLAGS = -c -ffreestanding -nostdlib -fno-builtin -fno-rtti -fno-exceptions
ASFLAGS = -c
CTMP = $(wildcard src/kernel/*.cpp)
ATMP = $(wildcard src/kernel/arch/i386/*.s)
CFILE = $(subst src/kernel/, ,$(CTMP))
AFILE = $(subst src/kernel/arch/i386/, ,$(ATMP))
CSRC = $(CFILE:.c=)
ASRC = $(AFILE:.s=)
OUT = $(wildcard out/*.o)
all: ccompile acompile link
ccompile:
for file in $(CSRC) ; do \
$(CC) $(CCFLAGS) src/kernel/$$file -o out/$$file.o ; \
done
acompile:
for file in $(ASRC) ; do \
$(AS) $(ASFLAGS) src/kernel/arch/i386/$$file.s -o out/$$file.o ; \
done
link:
ld $(LNFLAGS) -o latest.bin $(OUT)
Use the vpath directive to specifiy the source directories.
TARGETS := latest.bin
LD := ld
LDFLAGS := -T linker.ld -melf_i386
CC := ~/opt/cross/bin/i386-elf-g++
CCFLAGS := -c -ffreestanding -nostdlib -fno-builtin -fno-rtti -fno-exceptions
AS := ~/opt/cross/bin/i386-elf-as
ASFLAGS := -c
vpath %.cpp src/kernel
vpath %.s src/kernel/arch/i386
SOURCES := $(wildcard *.cpp) $(wildcard *.s)
OBJECTS := $(addsuffix .o, $(basename $(notdir $(SOURCES))))
all: $(TARGETS)
out/%.o: %.cpp
$(CC) $(CCFLAGS) -o $# $<
out/%.o: %.s
$(AS) $(ASFLAGS) -o $# $<
latest.bin: $(OBJECTS)
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C++ Make file issue "No rule to make target ..."

I just started working with makefile.
I am getting the error with makefile of my C++ project.
make: No rule to make target 'bin/smartCart_app', needed by all.
Below is the directory structure and files associated with it.
VBOX:~BASE$ls
build src
VBOX:~BASE$cd build
VBOX:~BASE/build$ ls
bin build Makefile.sc
VBOX:~BASE/build$ cd ../src
VBOX:~BASE/src$ls
baseStation.cpp config util //config and util has header and cpp files
Here is my Make file
CC=gcc
CPP=g++
CCFLAGS=-g -Wall -std=gnu+0x -o0
CC_LDFLAGS = -g -Wl
BUILD=./build
BIN = ./bin
SC_SRC_ROOT = ../src
SC_SRC_SUBDIRS = config util
SC_SRC_RELDIRS = $(addprefix $(strip $(SC_SRC_ROOT)), $(strip $(SC_SRC_SUBDIRS)))
SC_SRCS_ = $(shell /usr/bin/find $(SC_SRC_ROOT)/config $(SC_SRC_ROOT)/util -name "*.cpp")
SC_SRCS = $(SC_SRCS_) baseStation.cpp
SC_NEW_SRCS = $(notdir $(SC_SRCS))
SPACE :=
SPACE +=
INCLUDE = $(addprefix -I, $(SRC_RELDIRS))
VPATH = $(subst $(SPACE),:,$(SRC_RELDIRS)) $(subst $(SPACE),:,$(SC_SRC_RELDIRS))
SC_INCLUDE = $(addprefix -I, $(SC_SRC_RELDIRS))
SC_OBJS = $(SC_NEW_SRCS:%.cpp=$(BUILD)/%.o)
SC_DEPS = $(SC_OBJS:%.o=%.d)
# Ensure paths exist.
$(shell [ -d "$(BIN)" ] || mkdir -p $(BIN))
$(shell [ -d "$(BUILD)" ] || mkdir -p $(BUILD))
# Explicit rules.
.PHONY: all clean $(PHONY)
all: $(BIN)/smartCart_app
clean:
#echo "Cleaning..."
-#rm -f $(BIN)/smartCart_app $(SC_OBJS)
$(SC_OBJS): $(BUILD)/%.o: %.cpp
#echo "Compiling $(notdir $<)"
#$(CPP) $(CCFLAGS) $(INCLUDE) $(SC_INCLUDE) -MD -c -o $# $<
$(MACRO_DEPS):
-#rm -f $(patsubst %_ON.d,%_OFF.d,$#) $(patsubst %_OFF.d,%_ON.d,$#) $#
#touch $#
#$(ALL_OBJS): %.o: %.d
$(DEPS): $(BUILD)/%.d: %.cpp
#$(CC) $< -MM -MF $# $(INCLUDE)

How to implement cleanall in when a common make file is used

Hi I am using common makefile.inc for my project. For my src folders, I define a makefile which sets some variables and includes makefile.inc. I can also define DIRS= variable (sample #2) which will call make -C on each one of the directories specified there. This all works. However, I cannot get a "clean" or "cleanall" to work properly. If DIRS= is defined, I need a way to go through all the directories listed and call "make -C xxx clean". Any ideas?
Sample makefile #1
TYPE = exe
SOURCES = test.cpp
INCLUDES = -I. -I/usr/local/include -I../src
LIBS = -lpcre
OUT = test
include ../../makefile.inc
Sample makefile #2
DIRS = src test
include ../makefile.inc
makefile.inc
OBJS = $(SOURCES:.cpp=.o)
ifeq ($(CFG),)
CFG=debug
endif
ifeq ($(CFG),debug)
CXXFLAGS += -g -Wall -DNDEBUG
else
CXXFLAGS += -O2 -Wall
endif
all: dirs cfgcheck $(OUT)
.PHONY: clean cleanall all
cfgcheck:
ifneq ($(CFG),release)
ifneq ($(CFG),debug)
#echo "Error: Invalid CFG '$(CFG)'' (options: debug,release)"
#exit 1
endif
endif
#echo "Making '$(CURDIR)' CFG="$(CFG)
$(OUT): $(OBJS)
ifeq ($(TYPE),lib)
$(AR) rcs $(OUT) $(OBJS)
endif
ifeq ($(TYPE),exe)
$(CXX) -o $# $^ ${LDFLAGS} $(LIBS)
endif
-include $(OBJS:.o=.d)
%.o: %.cpp
$(CXX) -c $(INCLUDES) $(CXXFLAGS) $*.cpp -o $*.o
$(CXX) -MM $(CXXFLAGS) $*.cpp > $*.d
#cp -f $*.d $*.d.tmp
#sed -e 's/.*://' -e 's/\\$$//' < $*.d.tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $*.d
#rm -f $*.d.tmp
dirs: $(DIRS)
$(DIRS):
$(MAKE) -C $#
clean:
rm -f $(OUT) *.o *.d
I'd do something like this:
DIRS = src test
clean: TARG:=clean
clean: $(DIRS)
.PHONY: $(DIRS)
$(DIRS):
#$(MAKE) -C $# $(TARG)
If you don't like using the names of directories as phony targets, there are alternatives that are slightly more complicated...

make clean with implicit rules in makefile

hen I do make clean it complains about missing files. In particular it complains about mapnameserver.hthat is included in nstest.cc and nstime.cc.
I thought that doing make clean would ignore all other targets, even implicit ones.
What I want is to be able to do make clean and make vectornameserver without make complaining about the headers that nstest.cc and nstime.cc includes that I have not yet written. Is this possible?
Below is the files in the src dir
nameserverinterface.h
nstest.cc
nstime.cc
vectornameserver.cc
vectornameserver.h
And this is the Makefile
#
# Makefile for CPP
#
# Compiler and compiler options:
CC = /usr/local/bin/clang++
CXX = /usr/local/bin/clang++
CXXFLAGS = -c -pipe -O2 -Wall -W -ansi -pedantic-errors
CXXFLAGS += -Wmissing-braces -Wparentheses -Wold-style-cast
CXXFLAGS += -std=c++11 -stdlib=libc++ -nostdinc++
CXXFLAGS += -I/Users/einar/devel/libcxx/include/
LDFLAGS = -stdlib=libc++
LDLIBS = -L/Users/einar/devel/libcxx/lib/
SRCDIR = ../src
LIBDIR = ../lib
BINDIR = ../bin
DEPDIR = ../dep
VPATH = $(SRCDIR):$(LIBDIR):$(BINDIR):$(DEPDIR)
LIB_INSTALL =
BIN_INSTALL =
SRC = $(wildcard $(SRCDIR)/*.cc)
OBJ = $(notdir $(SRC:.cc=.o))
DEP = $(addprefix $(DEPDIR)/, $(notdir $(SRC:.cc=.d)))
PROGS = vectornameserver
MAKEDEPEND = $(CXX) -MM $(CPPFLAGS) -o $*.d $<
CP = /bin/cp
###
#
# Phony targets
#
###
.PHONY: all
all: $(PROGS)
.PHONY: folder_setup
folder_setup:
mkdir -p $(SRCDIR)
mkdir -p $(LIBDIR)
mkdir -p $(BINDIR)
mkdir -p $(DEPDIR)
.PHONY: clean
clean:
#$(RM) $(OBJ)
.PHONY: cleaner
cleaner:
#$(RM) $(OBJ)
#$(RM) $(PROGS)
#$(RM) $(DEP)
#$(RM) $(wildcard $(DEPDIR)/*.d*)
###
#
# Set up targets for program files in this section
# a rule should look like:
# program: obj1.o obj2.o ...
#
###
vectornameserver : vectornameserver.o
###
#
# In this section automatic dependencies are handled.
#
###
$(addprefix $(DEPDIR)/, %.d): %.cc
#set -e; rm -f $#; \
$(CXX) -MM $(CPPFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $#: ,g' < $#.$$$$ \
> $#; rm -f $#.$$$$
###
#
# Include the automatically generated dependency files
#
###
include $(DEP)
Thanks in advance.
The problem is that you have an include directive in the makefile. This implicitly makes all the included dependency files implicit targets that must be refreshed BEFORE the primary target can be run. It is those rules that are running the compiler and giving you the errors.
Since generally you don't want/need the dependency files if you're just doing a make clean, the usual thing is to wrap appropriate ifs around the include:
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(MAKECMDGOALS),cleaner)
-include $(DEP)
endif
endif
This will avoid trying to include the depfiles (and thus regenerate them) if you do make clean or make cleaner. In addition, the - prefix on the include supresses warnings about the depfiles not existing when you first run make (it will (re)generate them and reread the makefile and depfiles if need be.)