If statement using vhdl-counter - if-statement

Question

It'z DFF counter counts from 0 to 10, and from 10 to 0. There z switch to switch between Ascending/Descending. On of the guys in this website helped me to solve the if statement problem but it looks itz not allowed to use it outside the process , si if any one could help and have any idea to use when istead . would be perfect. using planahead to design this counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port(
clk, reset, pause: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
constant M: integer:=10;
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
process(clk, reset, pause)
begin
if(reset='1') then r_reg <=(others=>'0');
elsif pause = '1' then
r_reg<=r_reg;
elsif (clk'event and clk='1') then
r_reg<=r_next;
end if;
end process;
------------------------------------------------------------------------
if (inc_dec='1') then
if (r_reg=(M-1)) then
r_next <= (others=>'0');
else
r_reg+1;
end if;
elsif (inc_dec='0') then
if (r_reg=(M-10)) then
r_next <= to_unsigned(9, 4);
else
r_reg-1;
end if;
end if;
------------------------------------------------------------------------
--Output logic
q<= std_logic_vector(r_reg);
end arc_counter;
The error still the same :
[HDLCompiler 806] Syntax error near "if".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".

Answer 1

Notice your missing an port with mode in for inc_dec.
As mentioned in the comment your if statement isn't a concurrent statement and needs to go in a process.
Your increments and decrements for r_next aren't correct for VHDL.
The pause shouldn't be asynchronous It infers a latch following the r_reg register.
Fix all those and it looks something like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port (
clk: in std_logic;
reset: in std_logic;
pause: in std_logic;
inc_dec: in std_logic; -- ADDED
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
UNLABELED:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
r_reg <= r_next;
end if;
end process;
ADDED_PROCESS:
process (inc_dec, r_reg)
begin
if inc_dec = '1' then
if r_reg = 9 then -- r_reg = M - 1 then
r_next <= (others => '0');
else
r_next <= r_reg + 1; -- r_reg+1;
end if;
elsif inc_dec = '0' then
if r_reg = 0 then -- r_reg = M - 10 then
r_next <= to_unsigned(9, 4);
else
r_next <= r_reg - 1; -- r_reg-1;
end if;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end arc_counter;
And about now someone is bound to chime in and write that the two processes can be consolidated.
And that could look something like:
architecture foo of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
SINGLE_PROCESS:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
if inc_dec = '1' then
if r_reg = 9 then
r_reg <= (others => '0');
else
r_reg <= r_reg + 1;
end if;
elsif inc_dec = '0' then -- and this could be simply else
if r_reg = 0 then
r_reg <= to_unsigned(9, 4);
else
r_reg <= r_reg - 1;
end if;
end if;
r_reg <= r_next;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end architecture;
Subject to further improvements or alternate implementations.