I have a Makefile as :
CC = g++
#SNAP DEFINITIONS
SNAP = Snap-2.3
SNAPCORE = $(SNAP)/snap-core
GLIB = $(SNAP)/glib-core
CPPFLAGS += -I $(GLIB) -I $(SNAPCORE)
pagerank_debug.o: pagerank.cpp
$(CC) $(CPPFLAGS) -c pagerank.cpp -o pagerank_debug.o
pagerank.o: pagerank.cpp
$(CC) $(CPPFLAGS) -c pagerank.cpp
pr_debug: pagerank_debug.o $(SNAPCORE)/Snap.o
$(CC) -g pagerank_debug.o $(SNAPCORE)/Snap.o -o prd
pr: pagerank.o $(SNAPCORE)/Snap.o
$(CC) pagerank.o $(SNAPCORE)/Snap.o -o pr
.PHONY: clean
clean:
rm *.o prd
On executing make pr_debug, the code is compiled as :
g++ -I Snap-2.3/glib-core -I Snap-2.3/snap-core -c pagerank.cpp -o pagerank_debug.o
g++ -g pagerank_debug.o Snap-2.3/snap-core/Snap.o -o prd
I do not see any debug symbols. What could be a potential issue?
Updated Makefile( Still does not work )
#SNAP DEFINITIONS
SNAP = /Users/myth/Snap-2.3
SNAPCORE = $(SNAP)/snap-core
GLIB = $(SNAP)/glib-core
INCLUDE += -I $(SNAPCORE) -I $(GLIB)
CPPFLAGS += -c -g -Wall
pagerank_debug: pagerank_undirected.cpp
g++ $(INCLUDE) $(CPPFLAGS) pagerank_undirected.cpp -o pagerank_undirected.o
pr_debug: pagerank_debug
g++ -g pagerank_undirected.o $(SNAPCORE)/Snap.o -o pru
.PHONY: clean all
all: pr_debug
clean:
rm *.o pru
-g flag should be added when compiling, so add it to CPPFLAGS:
CPPFLAGS += -I $(GLIB) -I $(SNAPCORE) -g
Related
I want to create a makefile which runs program in C++ once with "CXXFLAGS = -std=c++11 -g -O3 -DTEST -fopenmp" and one time with: "CXXFLAGS = -std=c++11 -g -O3 -fopenmp"
at the end outputs two different files like P1-Test and P1. how can I edit this file?
CXX = g++
CXXFLAGS = -std=c++11 -g -O3 -fopenmp
ifdef code_coverage
GCOV_FLAG := -DTEST
else
GCOV_FLAG :=
endif
all: P1
#echo The program has been compiled
# implicit rule: create x from x.cpp
.cpp:
$(CXX) $(CXXFLAGS) $? -o $#
$(CXX) $(CXXFLAGS) $(GCOV_FLAG) $? -o $#
.PHONY: clean
clean:
$(RM) -r P1 *.dSYM
My suggestion:
CXX = g++
CXXFLAGS = -std=c++11 -g -O3 -fopenmp
all: P1 P1-Test
#echo The program has been compiled
# implicit rule: create x from x.cpp
.cpp:
$(CXX) $(CXXFLAGS) $? -o $#
.PHONY: clean
clean:
$(RM) -r P1 *.dSYM
P1: main.o second.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) -o "$#" $^
P1-Test: CXXFLAGS+=-DTEST
P1-Test: main.o second.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) -o "$#" $^
With sample sources:
File main.cpp
extern void foo(); // should be in second.h or something
int main() { foo(); }
File second.cpp
#include <cstdio>
void foo() {
#ifdef TEST
puts("TEST defined");
#else
puts("TEST not defined");
#endif
}
Results in
$ make -B
g++ -std=c++11 -g -O3 -fopenmp -o "P1" main.cpp second.cpp
g++ -std=c++11 -g -O3 -fopenmp -DTEST -o "P1-Test" main.cpp second.cpp
The program has been compiled
And of course the outputs:
./P1; ./P1-Test
TEST not defined
TEST defined
Alternative
If your .o files are really .PRECIOUS, you might want to build separate copies. Here I split into release/main.o and test/main.o:
CXX = g++
CXXFLAGS = -std=c++11 -g -O3 -fopenmp
all: P1 P1-Test
#echo The program has been compiled
test/%.o: CXXFLAGS+=-DTEST
test/%.o: %.cpp
mkdir -pv $(#D)
$(CXX) $(CXXFLAGS) $? -c -o $#
release/%.o: %.cpp
mkdir -pv $(#D)
$(CXX) $(CXXFLAGS) $? -c -o $#
.PHONY: clean
clean:
$(RM) -rfv P1 P1-Test *.dSYM release/ test/
P1: release/main.o release/second.o
P1-Test: test/main.o test/second.o
P1 P1-Test:
$(CXX) $(CXXFLAGS) -o "$#" $^ $(LDFLAGS)
Which gives:
mkdir -pv release
g++ -std=c++11 -g -O3 -fopenmp main.cpp -c -o release/main.o
mkdir -pv release
g++ -std=c++11 -g -O3 -fopenmp second.cpp -c -o release/second.o
g++ -std=c++11 -g -O3 -fopenmp -o "P1" release/main.o release/second.o
mkdir -pv test
g++ -std=c++11 -g -O3 -fopenmp -DTEST main.cpp -c -o test/main.o
mkdir -pv test
g++ -std=c++11 -g -O3 -fopenmp -DTEST second.cpp -c -o test/second.o
g++ -std=c++11 -g -O3 -fopenmp -o "P1-Test" test/main.o test/second.o
echo The program has been compiled
Following is my make file
CC = g++
CFLAGS = -Wall -c -fPIC
INCLUDES = -I${HOME}/ComingSoon/api/include
LFLAGs = -L${HOME}/ComingSoon/lib
LIB_DIR = ${HOME}/ComingSoon/lib
LIBS = -lapi
API_SRCDIR = ${HOME}/ComingSoon/api/source
API_SOURCE = $(wildcard ${HOME}/ComingSoon/api/source/*.cpp)
#API_SOURCE = $(shell find $(API_SRCDIR) -name '*.cpp')
API_OBJ_SOURCE = $(wildcard ${HOME}/ComingSoon/api/obj/*.o)
OBJS_DIR_API = ${HOME}/ComingSoon/api/obj/
OBJS = $(patsubst $(API_SRCDIR)/%.cpp,$(OBJS_DIR_API)%.o,$(API_SOURCE))
api: $(OBJS)
$(OBJS): $(API_SOURCE) Makefile
$(CC) $(CFLAGS) $(INCLUDES) $< -o $#
clean_api:
rm -rf ${HOME}/ComingSoon/lib/*.so
rm -rf ${HOME}/ComingSoon/api/obj/*.o
I want to complie all the source files in the source directory.
The make file is compiling as
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/multiply.o
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/add.o
But the output should be as follows
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/multiply.cpp -o /home/soumya/ComingSoon/api/obj/multiply.o
g++ -Wall -c -fPIC -I/home/soumya/ComingSoon/api/include /home/soumya/ComingSoon/api/source/add.cpp -o /home/soumya/ComingSoon/api/obj/add.o
The makfile is compiling the same source file to make two different object file. Where I am doing wrong?
What should I use in place of
$(OBJS): $(API_SOURCE) Makefile
Your API_SOURCE variable contains multiply.cpp add.cpp, so your rule comes out to:
$(OBJS): multiply.cpp add.cpp Makefile
$(CC) ... $< -o $#
So $< always expands to multiply.cpp. The correct way is to write a pattern rule:
$(OBJS_DIR_API)%.o: $(API_SRCDIR)/%.cpp Makefile
$(CC) ... $< -o $#
I have a project that contains a obj and a src subfolder.
When I run make with the following Makefile, it builds each .o with the same src.
CXX = g++
CXXINCDIRS = -I./ext/glui/include -I.
CXXLIBDIR = /usr/lib/
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include
BINDIR = ./bin
EXE = $(BINDIR)/brushwork
CXXFLAGS += -W -Wall -Wextra -Weffc++ -std=c++11 $(CXXINCDIRS)
SRC_CXX = $(wildcard $(SRCDIR)/*.cc)
OBJECTS_CXX = $(patsubst $(SRCDIR)/%.cc, $(OBJDIR)/%.o, $(SRC_CXX))
LIBRARY_CXX = -lglut -lGL -lGLU -L/usr/lib -lglui
$(OBJDIR)/%.o: $(SRCDIR)/%.cc
g++ -o $# -c $<
$(EXE): $(OBJECTS_CXX) | $(BINDIR)
$(CXX) $(CXXFLAGS) $(CXXINCDIRS) -o $# $^ $(CXXLIBDIR) $(LIBRARY_CXX)
$(OBJECTS_CXX): $(SRC_CXX) | $(OBJDIR)
$(CXX) $(CXXFLAGS) -c -o $# $<
$(OBJDIR)/%.o: $(SRC_CXX) $(INCDIR)/%.h | $(OBJDIR)
$(CXX) $(CXXFLAGS) -c -o $# $<
$(BINDIR) $(OBJDIR):
mkdir -p $#
When I run the command
make -B -n
I get
mkdir -p obj
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/tool.o src/tool.cc
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/base_gfx_app.o src/tool.cc
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/color_data.o src/tool.cc
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/main.o src/tool.cc
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/pixel_buffer.o src/tool.cc
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -c -o obj/brushwork_app.o src/tool.cc
mkdir -p bin
g++ -W -Wall -Wextra -Weffc++ -std=c++11 -I./ext/glui/include -I. -I./ext/glui/include -I. -o bin/brushwork obj/tool.o obj/base_gfx_app.o obj/color_data.o obj/main.o obj/pixel_buffer.o obj/brushwork_app.o /usr/lib/ -lglut -lGL -lGLU -L/usr/lib -lglui
I am not sure why each obj file is being built with the same src file.
I have tried $(SRCDIR)/%.cc but make complains that there is no recipe for $(SRCDIR)/%.cc
How can I have make build each src file it's respective src file?
For this:
$(OBJDIR)/%.o: $(SRC_CXX) $(INCDIR)/%.h | $(OBJDIR)
$(CXX) $(CXXFLAGS) -c -o $# $<
I think you need this:
$(OBJDIR)/%.o: $(SRCDIR)/%.cc $(INCDIR)/%.h
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $# $<
I'm not sure what this does:
$(OBJECTS_CXX): $(SRC_CXX) | $(OBJDIR)
$(CXX) $(CXXFLAGS) -c -o $# $<
I suspect you should remove it.
And I think you should also remove this:
$(OBJDIR)/%.o: $(SRCDIR)/%.cc
g++ -o $# -c $<
It looks like you had 3 different rules to build your objects (unless I read it wrong).
I have seen questions like these on SO but everyone has different answers and directory structures that aren't working for me.
My makefile:
CC = g++
DEBUG = -g -std=c++11
TARGET = main
OBJECT_FILES = BingResultSet.o main.o
INC_PATH = -I HTTPClientLib/include
LIB_PATH = -L HTTPClientLib/lib/
start: clean BingResultSet.o main.o
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) $(OBJECT_FILES) -o $(TARGET)
rm -f *.o
BingResultSet.o: BingResultSet.cpp BingResultSet.h
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) -c BingResultSet.cpp
main.o: main.cpp
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) -c main.cpp
clean:
rm -f $(OBJECT_FILES) $(TARGET)
My file structure:
/Desktop/DataMiner/.cpp, .h, and makefile
/Desktop/DataMiner/HTTPClientLib/include/HTTPClient.h
/Desktop/DataMiner/HTTPClientLib/lib/HTTPClient.a
What's the correct way to link my static lib in my makefile?
Here's my $0.02:
there was no static library involved. Assuming you meant the .o files
you mix dependencies and build rules, instead, avoid repeating build rules:
$(TARGET): $(OBJECT_FILES)
$(CXX) $(DEBUG) $(INC_PATH) $^ -o $# $(LIB_PATH)
%.o: %.cpp
$(CXX) $(DEBUG) $(INC_PATH) -c $< -o $#
You used CC for a C++ compiler. That's strange. Use CXX
You used LDFLAGS when you were just compiling
You hardcoded the source and destination paths. Instead use the automatic variables ($^, $< for source; $# for destination)
You tried to hardcode header dependencies. That's error-prone and messes up source specification (you don't want $^ to list .h files in your command line...). Instead, use gcc -MM¹ to generate the dependencies for you!
Next, do a conditional include of those dependencies:
.depends:
$(CXX) -MM $(CXXFLAGS) -c *.cpp > $#
-include .depends
It's usually handy to keep the .o files so you can speed up builds. Of course, this was not a good plan until you generated the header dependencies automatically. If you insist, you can comment the .PRECIOUS target. Intermediate targets are automatically deleted by GNU Make
Here's the integrated offering I ended up with:
CXX = g++
TARGET = main
OBJECT_FILES = BingResultSet.o main.o
INC_PATH = -I HTTPClientLib/include
LIB_PATH = -L HTTPClientLib/lib/
CPPFLAGS = -g -std=c++11
CPPFLAGS+= $(INC_PATH)
# standard derived flags:
CXXFLAGS+=$(CPPFLAGS)
LDFLAGS+=$(LIB_PATH)
start: .depends $(TARGET)
$(TARGET): $(OBJECT_FILES)
$(CXX) $(CXXFLAGS) $^ -o $# $(LDFLAGS)
%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $< -o $#
clean:
rm -f .depends $(OBJECT_FILES) $(TARGET)
# to keep the .o files:
.PRECIOUS: $(OBJECT_FILES)
.depends:
$(CXX) -MM $(CXXFLAGS) -c *.cpp > $#
-include .depends
On a very simple sample set of files you get:
$ make clean
rm -f .depends BingResultSet.o main.o main
$ make
g++ -MM -g -std=c++11 -I HTTPClientLib/include -c *.cpp > .depends
g++ -I HTTPClientLib/include -c BingResultSet.cpp -o BingResultSet.o
g++ -I HTTPClientLib/include -c main.cpp -o main.o
g++ -I HTTPClientLib/include BingResultSet.o main.o -o main -L HTTPClientLib/lib/
$ cat .depends
BingResultSet.o: BingResultSet.cpp BingResultSet.h
main.o: main.cpp BingResultSet.h
test.o: test.cpp
¹ (or similar, see man-page)
I have the following makefile:
CC = gcc
SRC = source1.c
EXE = source1
FLAGS = -fopenmp
all: $(src)
$(CC) -o $(EXE) $(SRC) $(FLAGS)
clean:
rm $(EXE)
How can I modify it so I can use multiple sources, some of them compiled with the flag -fopenmp, some of them compiled without. Thanks a lot.
This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2
You can define for example, EXTFLAGS=$(FLAGS) -fopenmp, and use EXTFLAGS for some rules.