I've coded the following lines in my Makefile:
PROJECTS = ExamsGenerator ExercisesImporter
VERSION = .v0.0
EXTENSION = .Exe
BINDIR = ../bin
CONFDIR = ../config
DATADIR = ../data
DOCDIR = ../doc
INCDIR = ../include
LIBDIR = ../lib
OBJDIR = ../obj
SRCDIR = ../src
INCDIRS = $(INCDIR:%=-I%)
CC = g++
CCVAR = -D__DATADIR__=\"$(DATADIR)\"
CFLAGS = -g -Wall $(shell root-config --cflags) $(INCDIRS)
LDFLAGS = -g -Wall $(shell root-config --ldflags)
LDLIBS = $(shell root-config --glibs)
MEG_DEP = Functions.h Parser.h Test.h
MEG_DEPS = $(patsubst %,$(INCDIR)/%,$(MEG_DEP))
MEI_DEP = Functions.h Parser.h Exercise.h
MEI_DEPS = $(patsubst %,$(INCDIR)/%,$(MEI_DEP))
MEG_OBJ = mainExamsGenerator.o Parser.o Test.o
MEG_OBJS = $(patsubst %,$(OBJDIR)/%,$(MEG_OBJ))
MEI_OBJ = mainExercisesImporter.o Parser.o Exercise.o
MEI_OBJS = $(patsubst %,$(OBJDIR)/%,$(MEI_OBJ))
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(MEG_DEPS) $(MEI_DEPS)
#echo "\nCreating object: $#"
$(CC) $(CCVAR) $(CFLAGS) -c -o $# $<
all: $(PROJECTS)
#echo "\n"
ExamsGenerator: $(MEG_OBJS)
#echo "\nLinking $#"
$(CC) $(CCVAR) $(CFLAGS) $(LDLIBS) -o $(BINDIR)/$(#)$(VERSION)$(EXTENSION) $^
ExercisesImporter: $(MEI_OBJS)
#echo "\nLinking $#"
$(CC) $(CCVAR) $(CFLAGS) $(LDLIBS) -o $(BINDIR)/$(#)$(VERSION)$(EXTENSION) $^
.SILENT:
.PHONY: clean
clean:
\rm -f $(BINDIR)/*$(EXTENSION) $(OBJDIR)/*.o *~ $(INCDIR)/*~ $(SRCDIR)/*~
I'm a Makefile newbie so I've picked up hints from several places and I'm probably not writing it in the most elegant way. I have few questions to improve them:
Do I really need to add $(OBJDIR)/%.o into the dependencies ?
Written in this way Parser.h is listed twice. Is it possible to rewrite this pattern rule to avoid it ? E.g., I don't want to recompile MEG stuff if Exercise.h is modified. New dependencies will be added and I'd like to manage them in a smart way.
Any other suggestion?
Thanks in advance for any help.
Bye...
No, you don't need (and don't want) to list a target as its own prerequisite. That doesn't make sense and cannot work.
$(patsubst %,prefix/%,$(var)) can be written as $(addprefix prefix,$(var)).
You might want to read Auto-Dependency Generation for a method to automatically generate the correct dependencies for .o files. It will help solve some of your problems.
If, however, you don't want to get that fancy then what you need to remember is that you need to list, for each target, all the files that that target depends on and no other files.
So
Parser.o presumably depends on (at least) Parser.h
So add $(OBJDIR)/Parser.o: $(INCDIR)/Parser.h
Exercise.o presumably depends on (at least) Exercise.h (and possibly also Parser.h?)
So add $(OBJDIR)/Exercise.o: $(INCDIR)/Exercise.h (or possibly $(OBJDIR)/Exercise.o: $(INCDIR)/Exercise.h $(INCDIR)/Parser.h)
etc...
Note that prerequisites combine from wherever they are found so the above suggested lines will combine with a $(OBJDIR)/%.o: $(SRCDIR)/%.cpp rule to form a full set of prerequisites for the given .o file.
Related
I have a simple project, whose folder structure is something like:
ls -R
.:
build include makefile src
./build:
./include:
myfunc.h
./src:
main.cpp myfunc.cpp
I want to compile the .cpp sources into .o object files, which should end into ./build folder. Using the GNUmake documentation and other sources (e.g. Proper method for wildcard targets in GNU Make), I wrote this makefile:
CXX := g++
CXXFLAGS += -I./include
CXXFLAGS += -Wall
OBJDIR := ./build
SRCDIR := ./src
PROGRAM = release
DEPS = myfunc.h
SRC = $(wildcard $(SRCDIR)/*.cpp)
OBJ = $(patsubst $(SRCDIR)/%.cpp, $(OBJDIR)/%.o, $(SRC))
all: $(PROGRAM)
$(PROGRAM): $(OBJ)
$(CXX) $(CXXFLAGS) -o $(PROGRAM) $(OBJ)
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(DEPS)
$(CXX) $(CXXFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm $(PROGRAM) $(OBJ)
But I get the error message: make: *** No rule to make target 'build/main.o', needed by 'release'. Stop.. I tried a lot of different ways but I cannot manage to have my .o files end up in the ./build directory. Instead, everything works if I put them in the root directory of the project. I can also make it work by specifying a rule for each object file, but I'd like to avoid that. What am I missing?
(I am using GNUmake version 4.3)
The problem is here:
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(DEPS)
$(CXX) $(CXXFLAGS) -c $< -o $#
See the $(DEPS)? That expands to myfunc.h. The compiler knows where to find that file (or would if this recipe were executed), because you've given it -I./include, but Make doesn't know where to find it (so it passes over this rule).
Add this line:
vpath %.h include
P.S. If you want to be really clean, you can add a variable:
INCDIR := ./include
CXXFLAGS += -I$(INCDIR)
vpath %.h $(INCDIR)
I had a working Makefile for small C++ applications that just had a couple of source code files inside a single folder that was also the output folder. Now I am trying to separate source and object files and ran into a problem. This is how my makefile looks right now, I'll go into detail where the problem occurs below.
CC = gcc
CXX = g++
RM = del
TARGET = plox.exe
CFLAGS = -Wall -ggdb -O3 $(INCLUDE)
CXXFLAGS = -std=c++11 -Wall -ggdb -O3 $(INCLUDE)
LDFLAGS = $(LIB) -lglfw3 -lopengl32 -lglu32 -lgdi32
INCLUDE = -I$(GLFW_INC) -I$(GLAD_INC)
LIB = -L$(GLFW_LIB)
SRC_DIR = src
BUILD_DIR = build
GLFW_DIR = d:/external/glfw-3.1
GLFW_INC = $(GLFW)/include
GLFW_LIB = $(GLFW)/lib64
GLAD = d:/external/glad-c
GLAD_INC = $(GLAD)/include
CXX_SOURCES = $(SRC_DIR)/%.cpp
CXX_OBJS = $(addprefix $(BUILD_DIR)/, $(CXX_SOURCES:.cpp=.o))
OBJS = $(CXX_OBJS) $(BUILD_DIR)/glad.o
all: $(TARGET)
$(TARGET): $(OBJS)
$(CXX) -o $# $^ $(LDFLAGS)
$(CXX_OBJS): %.o: $(SRC_DIR)%.cpp
$(CXX) $(CXXFLAGS) -c -o $# $<
$(BUILD_DIR)/glad.o: src/glad.c
$(CC) -c $(CFLAGS) -c -o $(BUILD_DIR)/glad.o $(SRC_DIR)/glad.c
.PHONY: clean
clean:
$(RM) $(TARGET) $(OBJS)
The problem is in the line:
$(CXX_OBJS): %.o: $(SRC_DIR)/%.cpp
Before my changes, it looked like this:
$(CXX_OBJS): %.o: %.cpp
A friend helped gave me a template and I never really knew what that line really does. In another thread I learned that this is a static pattern rule so I guess this is where I made the mistake. But writing it down just now, I think the error could be earlier already. I might have made a mistake when defining $(CXX_OBJS). Could it be that the objects in that list are of the form build/src/test.o instead of build/test.o?
But how can I fix the addprefix line to produce the correct output? And where does the error in the title come from; where am I mixing those? I thought it could be about the $(SRC_DIR) in the static pattern rule because I probably misunderstood how it worked, but omitting it doesn't make the error go away. Moreover (assuming CXX_OBJS is working correctly later), if the static pattern rule checks every file in the list $(CXX_OBJS) for a match with %.o, and then has a dependency on the same file with ending .cpp, then that is also not correct because of the build folder prefix.
All in all, I'm very confused about how to handle the folder prefixes correctly and any advice is greatly appreciated!
In a static pattern rule, the words in the first section (the targets) have to be real files. None of them can contain patterns (%). You have:
CXX_SOURCES = $(SRC_DIR)/%.cpp
CXX_OBJS = $(addprefix $(BUILD_DIR)/, $(CXX_SOURCES:.cpp=.o))
$(CXX_OBJS): %.o: $(SRC_DIR)%.cpp
So CXX_OBJS is $(BUILD_DIR)/$(SRC_DIR)/%.o, which contains a pattern, so this is illegal.
I don't really know what you're trying to do with CXX_SOURCES. Maybe you wanted:
CXX_SOURCES := $(wildcard $(SRC_DIR)/*.cpp)
instead?
In addition to MadScientist's correct answer, there was another error in my Makefile introduced by renaming variables: mingw32-make couldn't find the -lglfw3 part because I used $(GLFW) in the definition of GLFW_INC and GLFW_LIB, but didn't define it. I wanted to have $(GLFW_DIR) instead.
I'm trying to build multiple shared libraries in one makefile. This is what I'm using to build one shared library:
CC = gcc # C compiler
PWD := $(shell pwd)
CFLAGS = -fPIC -Wall -Wextra -O2 -g # C flags
LDFLAGS = -shared # linking flags
RM = rm -f # rm command
CFLAGS += $(DFLAGS)
TARGET_LIB := lib1.so # target lib
#TARGET_LIB += lib2.so
SRCS := lib1.c # source files
#SRCS += lib2.c # source files
OBJS = $(SRCS:.c=.o)
.PHONY: all
all: $(TARGET_LIB)
$(TARGET_LIB): $(OBJS)
$(CC) $(INC) $(LDFLAGS) $(CFLAGS) -o $# $^
However, I can't just uncomment the lines for lib2 and have it being built as well. It's likely because $(TARGET_LIB): $(OBJS) expands to lib1.so lib2.so : lib1.o lib2.o which isn't what I want.
Instead, I want something like
lib1.so : lib1.o
lib2.so : lib2.o
But I'm not sure how to do so or what it is called. Can someone tell me what to do to achieve what I'm looking for?
EDIT: I should have been more clear. I realize you can add more targets to build these. But is there a way to do it without having to write a new target everytime I want to add a new library?
Thanks.
You can do something like this -
all : lib1.so lib2.so
and provide rules to make lib1.so and lib2.so
You can separate sources of two libraries into different directories. It also may help in further maintenance of your libraries. Then use one make file which will trigger corresponding sub-makefiles. I may be better than one big makefile
You can do it by separating targets like this:
CC = gcc # C compiler
PWD := $(shell pwd)
CFLAGS = -fPIC -Wall -Wextra -O2 -g # C flags
LDFLAGS = -shared # linking flags
RM = rm -f # rm command
CFLAGS += $(DFLAGS)
TARGET_LIB1 = lib1.so # target lib
TARGET_LIB2 = lib2.so
TARGET_LIBS = $(TARGET_LIB1) $(TARGET_LIB2)
SRCS1 = lib1.c # source files
SRCS2 = lib2.c # source files
SRCS = $(SRCS1) $(SRCS2)
OBJS1 = $(SRCS1:.c=.o)
OBJS2 = $(SRCS2:.c=.o)
OBJS = $(OBJS1) $(OBJS2)
.PHONY: all
all: $(TARGET_LIBS)
$(TARGET_LIB1): $(OBJS1)
$(CC) $(INC) $(LDFLAGS) $(CFLAGS) -o $# $^
$(TARGET_LIB2): $(OBJS2)
$(CC) $(INC) $(LDFLAGS) $(CFLAGS) -o $# $^
The implicit rules are for that. Read about them in the GNU Make manual.
Replace
$(TARGET_LIB): $(OBJS)
with
%.so: %.c
i am having a hard time with the Makefile below. It always recompiles because it is looking for the objects in "source/" instead of "objects/".
Since i did not write that Makefile and don't know what all those options mean i can't figure out how to tell it to look for the objects in the correct folder.
TITLE =example_title
SRC_DIR = source/
OBJ_DIR = objects/
OUTDIR = build/
SRC := $(wildcard **/*.cpp)
OBJ := $(patsubst source/%.cpp,%.o,$(SRC))
FP_OBJ := $(patsubst %,objects/%,$(OBJ))
LIB = $(wildcard *.a) $(wildcard **/*.a)
CC =g++
LD =g++
CC_FLAGS = -m32 -c -Wall -g -o
EXECUTABLE = $(TITLE)
LD_FLAGS = -m32 -L/usr/lib32 -o $(OUTDIR)$(EXECUTABLE)
$(OUTDIR)$(EXECUTABLE) : $(OBJ)
$(LD) $(LD_FLAGS) $(FP_OBJ) $(LIB)
$(OBJ) : $(SRC)
$(CC) $(CC_FLAGS)$(OBJ_DIR)$# $(SRC_DIR)$*.cpp
$(TITLE).tar.gz : **/*.h **/*.cpp Makefile **/*.txt
tar -czf $# Makefile **/*.h **/*.cpp **/*.txt
dist: $(TITLE).tar.gz
all : $(OUTDIR)$(EXECUTABLE)
clean :
rm -f $(OBJ_DIR)*.o
rm -f $(OUTDIR)$(EXECUTABLE) $(TITLE).tar.gz
This should do it:
$(OUTDIR)$(EXECUTABLE) : $(FP_OBJ)
$(LD) $(LD_FLAGS) $^ $(LIB)
$(FP_OBJ) : $(OBJ_DIR)%.o : $(SRC_DIR)%.cpp
$(CC) $(CC_FLAGS) $# $<
The basic problem was here:
$(OBJ) : $(SRC)
$(CC) $(CC_FLAGS)$(OBJ_DIR)$# $(SRC_DIR)$*.cpp
Apart from the fact that $(OBJ) : $(SRC) makes each object depend on all sources, this rule promises foo.o and delivers objects/foo.o. So every time through, Make saw that there was no foo.o, and duly tried to rebuild it and the executable that required it.
There are other problems with this makefile, like the sloppy wildcards and the obnoxious practice of including slashes in the directory names, but they're not so serious.
I'm still quite new to make. I am trying to compile a project in which maketest.cpp and maketest.hpp rests on Users/wen/Projects/maketest with the Makefile itself. Problem is, I want to also compile and link the source files (.cc and .hh) in Users/wen/Projects/include/bigint.
# Macros
INCLUDE = -I/Users/wen/Projects/include/bigint
LIBS =
CC = g++
override FLAGS += -O2
HEADERS= $(wildcard *.hpp) $(wildcard Users/wen/Projects/include/bigint/*.hh)
# EXE Name
INSTALL = maketest
CC_FILES = %.cpp Users/wen/Projects/include/bigint/%.cc
OBJ_FILES = maketest.o $(wildcard Users/wen/Projects/include/bigint/*.o)
# Rules
$(INSTALL): $(OBJ_FILES)
$(CC) $(FLAGS) $^ -o $# $(LIBS)
%.o: $(CC_FILES) $(HEADERS)
$(CC) $(FLAGS) $(INCLUDE) -c $< -o $#
# Installation types
install: $(INSTALL)
release:
#echo "Re-run with parameter:"
#echo "FLAGS=-D_RELEASE"
debug:
#echo "Re-run with parameter:"
#echo "FLAGS=-D_DEBUG"
# Cleaning up
clean:
rm -f $(OBJ_FILES) $(INSTALL)
The code compiles maketest.cpp and links it, but not bigint.
What will be the right way to build and link the files from Users/wen/Projects/include/bigint? Many thanks!
I figured it out at the end, thank you Jay. The problem was I forgot a slash at the front of Users/wen/Projects/include/bigint, so it was not searching from root but instead the project folder. Now it works!
Try explicitly specifying one of the files from bigint in OBJ_FILES (perhaps "bigint.o" ?). I don't think your wildcard is getting what you want.