Makefile - Erro: file truncated - c++

i have a simple Makefile:
CC=g++
CFLAGS= -Wall -std=c++11 -M -MF dependencyFileName.d -c
objects = Table.o LimitedTable.o aDimension.o test.o
edit: $(objects)
g++ -o edit $(objects)
test.o: LimitedTable.o Table.o aDimension.o test.cpp
$(CC) $(CFLAGS) test.cpp -o test.o
LimitedTable.o: LimitedTable.cpp LimitedTable.hpp Table.o aDimension.o
$(CC) $(CFLAGS) LimitedTable.cpp -o LimitedTable.o
aDimension.o: aDimension.cpp aDimension.cpp Table.o
$(CC) $(CFLAGS) aDimension.cpp -o aDimension.o
Table.o: Table.cpp Table.hpp
$(CC) $(CFLAGS) Table.cpp -o Table.o
clean:
rm -f *.o
and I get this error:
marius#marius-Lenovo-Y50-70 ~/Documents $ make clean
rm -f *.o
marius#marius-Lenovo-Y50-70 ~/Documents $ make edit
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c Table.cpp -o Table.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c aDimension.cpp -o aDimension.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c LimitedTable.cpp -o LimitedTable.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c test.cpp -o test.o
g++ -o edit Table.o LimitedTable.o aDimension.o test.o
Table.o: file not recognized: File truncated
collect2: error: ld returned 1 exit status
make: *** [edit] Error 1
Can anyone tell me what is wrong ?
Could a wrong include in one of the files be a reason for this error ?

There are some problems with the way you handle your dependency file, but first:
I have a simple Makefile
No you don't. The amount of boilerplate code is way too high, and adding any file to your projet will require you to manually edit that makefile again.
Your Makefile should be boiled down to this:
SRC := $(wildcard *.cpp)
OBJ := $(SRC:.cpp=.o)
DEP := $(OBJ:.o=.d)
CPPFLAGS := -MMD -MP
CXXFLAGS := -std=c++11 -Wall
edit: $(OBJ)
$(CXX) $^ -o $#
-include $(DEP)
clean:
$(RM) $(OBJ) $(DEP)
Here you :
avoid repeating yourself too much,
make good use of make's implicit rules to save time,
use the right built-in variables instead of overriding the wrong ones,
correctly handle dependency files creation and actually use them to prevent manual recompilation,
won't need to edit the makefile when adding a .cpp or .hpp file to your project.
Also, that should fix your problem. Don't forget to clean before trying to compile again after such an error ("file truncated") occurred.

Related

how do I set compilingflags in a makefile?

I'm used to program in IDEs, but switched to vim and plugins recently. Now I try to write a makefile for a c++ project, but somehow if I run make I always get the error
g++ -c -o *.o createOutput.cpp
In file included from /usr/include/c++/4.8/thread:35:0,
from createOutput.cpp:5:
/usr/include/c++/4.8/bits/c++0x_warning.h:32:2: error: #error This file requires compiler and library support for the ISO C++ 2011 standard. This support is currently experimental, and must be enabled with the -std=c++11 or -std=gnu++11 compiler options.
#error This file requires compiler and library support for the \
^
This is my makefile:
CC = clang++
# compiler flags
CFLAGS = -O3 -Wall -Werror -std=c++11
CFLAGS_SFML = -lsfml-graphics -lsfml-window -lsfml-system
all: program.exe clean
program.exe: *.o
$(CC) -o program.exe *.o $(CFLAGS) $(CFLAGS_SFML)
getInput.o: getInput.cpp
$(CC) -c getInput.cpp $(CFLAGS)
createOutput.o: createOutput.cpp
$(CC) -c createOutput.cpp $(CFLAGS)
main.o: main.cpp
$(CC) -c main.cpp $(CFLAGS)
.PHONY: clean
clean:
rm *.o
#echo clean done
Where is my error? Why is it using g++ instead of clang? And why isn't it using the -std=c++11 parameter? Sorry for the beginner questions, I unfortunately can't find a solution with google.
You want to set CXXFLAGS, that gets picked up automatically by make (and sent to your compiler (eg g++, clang++, etc).
make tried to make target '*.o'.
So, instead of that, you can specify sources list explicitly:
CC = clang++
#compiler flags
CFLAGS = -O3 -Wall -Werror -std=c++11
CFLAGS_SFML = -lsfml-graphics -lsfml-window -lsfml-system
SRCS = getInput.cpp createOutput.cpp main.cpp
OBJS = $(SRCS:.cpp=.o)
all: program.exe
program.exe: $(OBJS)
$(CC) -o program.exe *.o $(CFLAGS) $(CFLAGS_SFML)
getInput.o: getInput.cpp
$(CC) -c getInput.cpp $(CFLAGS)
createOutput.o: createOutput.cpp
$(CC) -c createOutput.cpp $(CFLAGS)
main.o: main.cpp
$(CC) -c main.cpp $(CFLAGS)
.PHONY : clean
clean:
rm *.o
#echo clean done
Note definition of variables OBJS and SRCS.

c++ undefined reference to `main' while compiling

After try to use this attached makefile the error that appears is :
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
make: *** [Ass1F] Error 1
the makefile is :
all: Ass1F
Ass1F: bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
g++ -o bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
#echo 'Finished building target: Ass1F'
#echo ' '
bin/x.o: src/x.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/x.o src/x.cpp
bin/y.o: src/y.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/y.o src/y.cpp
bin/z.o: src/z.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/z.o src/z.cpp
bin/w.o: src/w.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/w.o src/w.cpp
bin/main.o: src/main.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/main.o src/main.cpp
clean:
rm -f bin/*
what should I do with this problem?
the reason is the makefile or something in the code?
just to let you know we used eclipse to write the code and everything work perfectly- no any bugs.
thanks
Line g++ -o bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o tries to create executable named bin/main.o, overwriting its previous contents.
It should be e.g. g++ -o Ass1F bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
Your makefile recipe for Ass1F is incorrect, it doesn't specify the output file, os make uses bin/main.o as the output file instead of one of the input files.
You can simplify the makefile by using pattern rules (i.e. with wildcards) and using pre-defined variables such as $# (the name of the target) and $^ (the list of prerequisites) and CXX (the C++ compiler):
CXXFLAGS = -g -Wall -Weffc++
CPPFLAGS =
LDFLAGS =
LDLIBS =
all: Ass1F
Ass1F: bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
$(CXX) $(LDFLAGS) -o $# $^ $(LDLIBS)
#echo 'Finished building target: Ass1F'
#echo ' '
bin/%.o: src/%.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $^
clean:
rm -f bin/*

Makefile generate dependency automatically does not work

I have four cpp files and so many .h files. I expect my make file generates the appropriate .d file for each .cpp file and compiles them to .o and then links them. Could some one tell me what is wrong with this code? it does not work in the way that it should.
Btw, I am beginner in makefile! Please do not link to somewhere with hard explanation for highly experts.
$make
g++ -c -g -Wall -Wconversion -Wfatal-errors -Wextra -std=c++11 -MD -MP -MF ./bin/obj/app/sim_rhs.d -o bin/obj/app/sim_rhs.o app/sim_rhs.cpp
app/sim_rhs.cpp:49:1: fatal error: opening dependency file ./bin/obj/app/sim_rhs.d: No such file or directory
}
^
compilation terminated.
make: *** [bin/obj/app/sim_rhs.o] Error 1
Cpp Files:
main.cpp
app/sim_rhs.cpp
app/sim_mids.cpp
app/sim_outputs.cpp
Makefile
SOURCES := main.cpp app/sim_rhs.cpp app/sim_mids.cpp app/sim_outputs.cpp
OUTDIR:= ./out
BINDIR:= ./bin
OBJDIR:= ./bin/obj
OBJECTS := $(addprefix $(OBJDIR)/,$(SOURCES:.cpp=.o))
DEPFILES:= $(OBJECTS:.o=.d)
CXX := g++
CXXFLAGS := -c -g -Wall -Wconversion -Wfatal-errors -Wextra -std=c++11 -MD -MP
LIBS:= -lboost_filesystem -lboost_system
# default
%:: $(BINDIR)/sim
# Link the executable
$(BINDIR)/sim: $(OBJECTS)
$(CXX) $(LDFLAGS) $^ -o $# $(LIBS)
run:
$(BINDIR)/sim
$(OBJDIR)/%.o: %.cpp
$(CXX) $(CXXFLAGS) -MF $(OBJDIR)/$*.d -o $# $<
-include $(DEPFILES)
Please avoid duplicate suggestion as I have an existing code. I do not want any other person's makefile template.

OpenMP Makefile, -fopenmp won't work

I'm trying to compile my project using a Makefile, but somehow the -fopenmp flag won't work.
Here's the Makefile:
TARGET=isaac
CC=g++
CFLAGS=-Wall -O2 -fopenmp
LDFLAGS=-lm -lpthread -lrt
OBJ=src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o
isaac: $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
clean:
rm src/*.o src/*~ isaac
and here is the output when calling "make"
g++ -c -o src/main.o src/main.cpp
g++ -c -o src/bhtree.o src/bhtree.cpp
g++ -c -o src/body.o src/body.cpp
g++ -c -o src/configreader.o src/configreader.cpp
g++ -c -o src/diagnostics.o src/diagnostics.cpp
g++ -c -o src/output.o src/output.cpp
g++ -c -o src/quad.o src/quad.cpp
g++ -c -o src/timing.o src/timing.cpp
g++ -c -o src/vector2.o src/vector2.cpp
g++ -Wall -O2 -fopenmp -o isaac src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o -lm -lpthread -lrt
the -fopenmp flag is missing when the source files are compiled, so the finished executable is serial, not parallel.
How can I fix this?
The problem is that your rule does not apply at all. You are free to remove
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
and you'll get the same result as before. That's because some predefined rule is used instead of yours (I'm not great makefile expert though).
The core of the problem is that your rule is for ./*.o files, but you need ./src/*.o for isaac. You can change your rule
src/%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
Or (better) move all autogenerated staff somewhere from src.

Makefile - wildcard, how to do that properly?

FLAGS:= -Wall -Wvla -g -lm
OBJECT := Nominated.h UniversityNominated.h AliceGraduate.h BobGraduate.h CollegeNominated.h ColinGraduate.h DannyGraduate.h NominatedList.h Parser.h Parser.cpp
all: Hire
Nominated.o: Nominated.h Nominated.cpp
g++ -c $(FLAGS) Nominated.cpp -o Nominated.o
NominatedList.o: Nominated.h NominatedList.h NominatedList.cpp
g++ -c $(FLAGS) NominatedList.cpp -o NominatedList.o
UniversityNominated.o: Nominated.h UniversityNominated.h UniversityNominated.cpp
g++ -c $(FLAGS) UniversityNominated.cpp -o UniversityNominated.o
AliceGraduate.o: Nominated.h UniversityNominated.h AliceGraduate.h AliceGraduate.cpp
g++ -c $(FLAGS) AliceGraduate.cpp -o AliceGraduate.o
BobGraduate.o: Nominated.h UniversityNominated.h BobGraduate.h BobGraduate.cpp
g++ -c $(FLAGS) BobGraduate.cpp -o BobGraduate.o
CollegeNominated.o: Nominated.h CollegeNominated.h CollegeNominated.cpp
g++ -c $(FLAGS) CollegeNominated.cpp -o CollegeNominated.o
ColinGraduate.o: Nominated.h CollegeNominated.h ColinGraduate.h ColinGraduate.cpp
g++ -c $(FLAGS) ColinGraduate.cpp -o ColinGraduate.o
DannyGraduate.o: Nominated.h CollegeNominated.h DannyGraduate.h DannyGraduate.cpp
g++ -c $(FLAGS) DannyGraduate.cpp -o DannyGraduate.o
Parser.o: $(OBJECT)
g++ -c $(FLAGS) Parser.cpp -o Parser.o
Parser: Nominated.o UniversityNominated.o AliceGraduate.o BobGraduate.o CollegeNominated.o ColinGraduate.o DannyGraduate.o NominatedList.o Parser.o
ar rcu libParser.a Nominated.o UniversityNominated.o AliceGraduate.o BobGraduate.o CollegeNominated.o ColinGraduate.o DannyGraduate.o NominatedList.o Parser.o
ranlib libParser.a
Hire: Hire.cpp Parser
g++ Hire.cpp libParser.a -o Hire
clean:
rm -f Hire *.a *.o *~
.PHONY: clean all
so this is my Makefile.
How can I make less ugly ?
I am always read about that but I can not get the idea
How ?
I mean I understand I need to use the wildcard tool but as you I probably used it wrong
Here's an example of how to use wildcard and pattern substitution:
SOURCES := $(wildcard *.cpp)
OBJECTS := $(patsubst %.cpp,%.o,$(SOURCES))
CXX := g++ -Wall -Wvla -g
.cpp.o:
${CXX} -c $<
This will build all the .cpp files into their object files.
There's many things you can do, but one of the best is a pattern rule for specific types. All of your objects seem to be built the same way.
%.o: %.cpp
${CXX} -c $(FLAGS) -o $# $<
You'll notice that this doesn't include any header files as dependencies. Manually maintaining the header dependencies in a Makefile is a bad idea because it's bound to get out of date as you modify your program. Sometimes your compiler can generate make-friendly dependencies for you automatically. Assuming you have a list of objects such as this:
OBJS := $(SOURCES:%.c=%.o)
You can include this at the very end of your Makefile (with no blank line afterward)
-include $(OBJS:.o=.d)
Then add, -MMD to your compiler flags. This will cause GCC to generate .d files that contain the header dependencies for each of your objects as a Make rule, and the above include line will include those rules and use them to resolve the dependencies of your objects. This will mean that any header change will cause all files that include it (directly or indirectly) to be rebuilt.
Try this:
FLAGS = -Wall -Wextra
SRC = $(wildcard *.cpp)
OBJ = $(patsubst %.cpp,%.o,$(SRC))
DEP = $(patsubst %.cpp,%.d,$(SRC))
PARSER = $(filter-out Hire.o,$(OBJ))
all: $(DEP) build
build:
make Hire
%.d:
g++ -MM $*.cpp > $*.d
%.o: %.cpp
g++ $(FLAGS) -c $*.cpp
libParser.a: $(PARSER)
ar rcu libParser.a $(PARSER)
ranlib libParser.a
Hire: Hire.cpp libParser.a
g++ Hire.cpp libParser.a -o Hire
clean:
rm -f Hire *.a *.o *.d *~
.PHONY: clean all
#
# This line includes all the dependencies.
# There is one for each file.
# Check the *.d files after you run make
-include $(DEP)