I have main.cpp file for which I want to generate dependency file main.d (to be included in Makefile).
I'm calling g++ -MM -MF src/main.d -MP -MT src/main.o src/main.cpp. It works fine unless I have some source generator. I found -MG flag for this, but it doesn't work as I expected it to work.
For example: main.cpp includes module/mod.h (#include "module/mod.h") and mod.h includes generator/gen.h (#include "generator/gen.h"), gen.h is generated. There is following structure:
-Makefile
-src
--main.cpp
--module
---mod.h
---generator
----gen.h
In Makefile I have a rule to generate src/module/generator/gen.h.
Generated by g++ dependencies for existing files are correct:
src/main.o: src/module/mod.h
But for non-existing file gen.h dependency is just generator/gen.h.
If I generate this file before generating dependencies it is correct src/module/generator/gen.h.
Is there any other option for g++ to correctly generate dependencies for non-existing files?
main.d generated when gen.h doesn't exist:
src/main.o: src/module/mod.h generator/gen.h
Correct main.d generated when gen.h exist:
src/main.o: src/module/mod.h src/module/generator/gen.h
As stated in man gcc
The dependency filename is taken directly from the "#include" directive without prepending path
actually there's no way for gcc to know the real path.
I'd recommend you to fix the include statement to keep include path in sync with make path, i.e. white in mod.h
#include <module/generator/gen.h>
put Makefile to src and add proper -I flag to gcc, e.g.
SRCDIR := $(shell pwd)
CXXFLAGS += -I$(SRCDIR)
it is a good practice to always start all non-local includes from some 'source root'
Related
I have the following question. After a successful compilation, if I compile it again after I only change some content in one of the .h files, the computer says:
make: Nothing to be done for `all'.
Can I force the compiler to compile again even if I have only modified the .h files?
If you want your output to be updated when header files change, then you have to add it to your dependency statement:
myprogram: myprogram.cpp myprogam.h
c++ -o myprogram myprogram.cpp
Typically we don't do it this way because the code that does things stays in the cpp file. If you are on unix and want to force a rebuild, just touch a cpp file to update its timestamp (forcing a rebuild) with "touch myprogram.cpp", for example, or delete your existing executable.
If you are using make without a Makefile, letting it infer dependencies, it will probably not infer the header dependencies. In this case, either blow away your executable or touch your source file.
Sounds like your Makefile does not have dependencies configured correctly. That is what you should look into fixing.
If you really want to just force a rebuild rather than fix the underlying problem. Then you can do a make clean before your make all or, if the Makefile does not have a "clean" target, delete all the generated object files and libs/executables and then run make all again.
You can force make to rebuild everything using the --always-make command line option.
However, it sounds like you don't have your dependencies setup properly in your Makefile. If your code (.cpp files) actually include headers, then generally your target for compiling them should have a prerequisite on the header files that it includes.
There is a simpler way than the accepted answer. Simply add -MD to your compiler flags in your Makefile, and -include myfile.d at the end of the Makefile (listing all source files with a *.d extension instead). This will, respectively, generate and reference additional *.d dependency files in your build folder (wherever your *.o files go) when you make, so you do not need to explicitly add every single header file to your makefile dependencies.
This is useful for projects with a long list of header files. Furthermore, this way, you know that you can't forget to include a header file in your Makefile dependencies, preventing troubleshooting time lost later when you think your binary updated when you changed a header file, but it actually didn't because you forgot to put it in the Makefile.
For example, use gcc -MD -I. -c myfile.cpp -o obj/myfile.o, and you can keep your Makefile dependencies as just foo: myfile.cpp without myfile.h.
A shortcut way to do this so you only need to list all files once is something like the following:
# Beginning of Makefile etc. etc.
# Only need to list all files once, right here.
SRCS = myfile.cpp myfile2.cpp
OBJS = $(SRCS:%.cpp=%.o)
# put .o and .d files in ./obj/
# (Assumes 'obj' directory exists)
FULLOBJS = $(addprefix obj/,$(OBJS))
# rule to make object (*.o) files
$(FULLOBJS): obj/%.o:%.cpp
gcc -MD -I. -c %< -o $#
# rule to make binary
foo: $(FULLOBJS)
g++ -o $# $(FULLOBJS)
# rule to clean (Note that it also deletes *.d files)
.PHONY: clean
clean:
rm -rf obj/*.o obj/*.d foo
# include dependency files (*.d) if available
-include $(FULLOBJS:%.o=%.d)
Can I force the compiler to compile again even if I have only modified
the .h files?
Yes ... but you probably want to improve your make (tool).
What I do is to force the most recent compile of the file in question, where the command generated by make shows.
Example:
# ... noise
g++ -O3 -ggdb -std=c++14 -Wall -Wextra -Wshadow -Wnon-virtual-dtor -pedantic -Wcast-align -Wcast-qual -Wconversion -Wpointer-arith -Wunused -Woverloaded-virtual -O0 lmbm101_11.cc -o lmbm101_11 -L../../bag -lbag_i686 -lnet_i686 -lposix_i686 -lzlib_i686 -lrt -pthread
# ... more noise.
To force a build, I highlight the "command" make created (starts with "g++", and resides between noise and more noise), and invoke it instead of make.
This is trivial using emacs on Linux. Might not be so easy on other systems.
You might consider copying this command into the file, for future use.
( i.e. I bypass make until I choose to fix my make file. )
A Makefile in the subdirectory of my project doesn't see the include path ONLY when it is used from the main Makefile of my project. I don't have much experience with Makefiles and a lot of what I've been reading is pretty confusing. Here is the layout of my directory (with what I have so far since I just started the project):
main/
Inventory/
Item.h
Item.cpp
Makefile
tools/
include/
json/
json.h
jsoncpp.cpp
Makefile
main.cpp
Makefile
Here is the Makefile in the main directory:
INCLUDE = -IInventory/
CC = g++
DEP = tools/jsoncpp.o Inventory/Item.o
Main: main.o $(DEP)
cd tools/ && make
cd Inventory/ && make
$(CC) -o Main main.o $(DEP) $(INCLUDE)
main.o main.cpp
$(CC) -c main.cpp $(INCLUDE)
Here is the Makefile in the tools directory:
INCLUDE = -Iinclude/
CC = g++
jsoncpp.o: jsoncpp.cpp
$(CC) -c jsoncpp.cpp $(INCLUDE)
When I call make from the tools/, it works just fine. But when I call make from the main directory I get this error:
g++ -c -o tools/jsoncpp.o tools/json.cpp
tools/jsoncpp.cpp:76:23: fatal error: json/json.h: No such file or directory
#include "json/json.h"
^
compilation terminated.
Now I partially believe that it can't find the include directory for whatever reason, but the first line in that error is fairly odd to me because of that weird gap between g++ and -c. Since my project will soon get pretty big, how can I fix this?
If it's in -I directive, it should be #include <json/json.h> otherwise #include "include/json/json.h"
EDIT: Include directory is taken from current directory, so in main/ you have to use -Itools/include
Solution: Implicit rules were used so correct variable CXXFLAGS+=$(INCLUDE) must be set for compilation. See: make manual
And the main problem is Main: main.o $(DEP) - files in DEP must exist already otherwise it'll use implicit rules. Later after that cd tools/ && make is done.
#include <json/json.h> <- preprocessor will search in all includes paths
see gcc Include Syntax :
#include <file> This variant is used for system header files. It searches for a file named file in a standard list of system
directories. You can prepend directories to this list with the -I
option (see Invocation).
#include "file" This variant is used for header files of your own program. It searches for a file named file first in the directory
containing the current file, then in the quote directories and then
the same directories used for . You can prepend directories to
the list of quote directories with the -iquote option.
How does the gcc decide what files are to be listed as dependencies to an object file being produced, when it writes a .d file?
I'm seeing different .d files when sysroot path is absolute, and relative.
g++ --MMD --sysroot=absolute_path_to_sysroot -c -o file.o -MF file.d file.cpp
g++ --MMD --sysroot=relative_path_to_sysroot -c -o file.o -MF file.d file.cpp
I'm seeing a weird case, where,
If the compiler path and --sysroot are absolute, then 2 additional header files are being listed as dependencies in the .d file.
If the --sysroot is relative, then 2 additional header files are not being listed as dependencies in the .d file anymore.
This made me wonder, what is the criterion, other than a header being #included, based on which, the .d files are actually written by the compiler, and how would sysroot affect this?
As far as I can tell, it is based on the actual directory where the file is found
The actual "make this a dependancy" happens here, where sysp is set a few lines above based on the directory that it is found in.
http://gcc.gnu.org/viewcvs/gcc/trunk/libcpp/files.c?revision=206293&view=markup#l884
sysp gets set here:
http://gcc.gnu.org/viewcvs/gcc/trunk/gcc/incpath.c?revision=206289&view=markup#l446
Now, it gets complicated if the same directory is both in -I and -isystem directories. In that case, it gets determined by whether the file is included with #include <name> or #include "name" - those using <> are selected only if you use -MD or -M, etc, where the -MMD will ignore anything using <> (or in a directory marked with sysp).
I'm trying to modify and compile uvccapture on the Raspberry Pi. I got the source from here (it's just a few files).
(I think) the only external files it needs are those of jpeglib which I downloaded from here.
When compiling, where do I put the jpeglib source files? UVCCapture has the following line:
#include <jpeglib.h>
Does that mean I should put the jpeglib source files in the same directory as the UVCCapture source files? That seems messy. How can I set up the compiler (modify the Makefile?), and where should I put the jpeglib files so that I don't need to change the uvccapture include file lines?
And a side question, how come it only includes the .h file and not the .c file? (I'm pretty new to C/C++)
Here is the Makefile:
CC=gcc
CPP=g++
APP_BINARY=uvccapture
VERSION = 0.4
PREFIX=/usr/local/bin
WARNINGS = -Wall
CFLAGS = -std=gnu99 -O2 -DLINUX -DVERSION=\"$(VERSION)\" $(WARNINGS)
CPPFLAGS = $(CFLAGS)
OBJECTS= uvccapture.o v4l2uvc.o
all: uvccapture
clean:
#echo "Cleaning up directory."
rm -f *.a *.o $(APP_BINARY) core *~ log errlog
install:
install $(APP_BINARY) $(PREFIX)
# Applications:
uvccapture: $(OBJECTS)
$(CC) $(OBJECTS) $(XPM_LIB) $(MATH_LIB) -ljpeg -o $(APP_BINARY)
Thanks
The source file (uvccapture.c) doesn't care where the header file (jpeglib.h) is -- at least it shouldn't. The compiler must be told where to look for header files; traditionally, the header files go in some directory like inc_files/, and the compiler is invoked with a command like
gcc -blah -blah -blah -Iinc_files -c -o uvccapture.o uvccapture.c
If you use Make, then Make should execute a command like that. So either edit the makefile, or put the header files in the current directory.
The sane way to use #include in C/C++ is to have source files and header files include header files. That is, in foo.c there will be a couple of lines like:
#include <bar>
#include "baz.h"
and in baz.h there might be a few lines like:
#include <vector>
#include "qux.h"
You almost never see #include foo.c, because it's almost never a good idea.
I want to include GeometricRecognizer.cpp into run.cpp , I have the solution(below mentioned) for CMake which works, i want to include it in another project which uses make the format of makefile is also given below .How to add the dependency of GeometricRecognizer.cpp using makefile ?
CMake:
ADD_EXECUTABLE(run run.cpp lib/GeometricRecognizer.cpp)
TARGET_LINK_LIBRARIES(run)
Make :
INCS_GTK=-I/usr/include/gtk-2.0 -I/usr/include/glib-2.0 -I/usr/include/atk-1.0 -I/usr/include/cairo -I/usr/include/gdk-pixbuf-2.0
INCS=-I/usr/include/freetype2 -I/usr/include/mysql -Iframeworks ${INCS_GTK}
LDLIBS=-lconfig++ -lcxcore -lcv -lGL -lGLU -lglut
This line in a CMake file does not include a cpp file in another cpp file:
ADD_EXECUTABLE(run a.cpp b.cpp)
It creates an executable target called run which is the result of compiling a.cpp and b.cpp and linking those files.
In your Makefile the following lines:
MAINCXX=${shell find -name '*.cxx'}
TARGETS=${MAINCXX:%.cxx=%}
Are the two important lines which actually setup the executable targets to compile and which source files they are created from. As can be seen in those two lines MAINCXX is just a list of all files *.cxx in the source tree and TARGETS will be the same list just without the .cxx part (so if MAINCXX=run.cxx then it will be TARGETS=run.cxx)
Your makefile seems to be heavily designed to support that specific usecase, also the real Make magic happens in the last line of Makefile where it includes another Makefile.
You need to look at the file named generic.mk and understand how it is designed. If you just want to add another target you can add the following:
run: run.cpp lib/GeometricRecognizer.cpp
g++ -o run $(DEFINES) $(INCS) $(WARNINGS) run.cpp lib/GeometricRecognizer.cpp
The listing of source files can be replaced by a builtin variable in GNU Make.