VHDL If problems - if-statement

Question

I am trying to learn VHDL, and it is not going that well..
I wrote this piece of code,
library IEEE;
use IEEE.bit_1164.ALL;
use IEEE.bit_ARITH.ALL;
use IEEE.bit_UNSIGNED.ALL;
entity Switch_led is
port(
Switch_0: in bit;
Switch_1: in bit;
Switch_2: in bit;
Switch_3: in bit;
Switch_4: in bit;
Switch_5: in bit;
Switch_6: in bit;
Switch_7: in bit;
Led_0: out bit;
Led_1: out bit;
Led_2: out bit;
Led_3: out bit;
Led_4: out bit;
Led_5: out bit;
Led_6: out bit;
Led_7: out bit
);
end Switch_led;
architecture Behavioral of Switch_led is
begin
if Switch_0 = '1' then
Led_0 <= 1;
elsif Switch_1 = '1' then
Led_1 <= 1;
elsif Switch_2 = '1' then
Led_2 <= 1;
elsif Switch_3 = '1' then
Led_3 <= 1;
elsif Switch_4 = '1' then
Led_4 <= 1;
elsif Switch_5 = '1' then
Led_5 <= 1;
elsif Switch_6 = '1' then
Led_6 <= 1;
elsif Switch_7 = '1' then
Led_7 <= 1;
end if;
end Behavioral;
For some reason i get errors to my if statements in my architecture. But I aren't able to find what the mistake is. I hope the code makes sense.

Answer 1

The enumeration names for type bit are given in package standard.
type BIT is ('0', '1');
These sort of assignments:
Led_0 <= 1;
Should look like:
Led_0 <= '1';
You'll also note that an if statement is used in a place suitable for a sequential statement, meaning all those should be in a process statement.
SWITCH:
process (Switch_0,Switch_1,Switch_2,Switch_3,Switch_4,Switch_5, Switch_6,Switch_7)
begin
if Switch_0 = '1' then
Led_0 <= '1';
elsif Switch_1 = '1' then
Led_1 <= '1';
elsif Switch_2 = '1' then
Led_2 <= '1';
elsif Switch_3 = '1' then
Led_3 <= '1';
elsif Switch_4 = '1' then
Led_4 <= '1';
elsif Switch_5 = '1' then
Led_5 <= '1';
elsif Switch_6 = '1' then
Led_6 <= '1';
elsif Switch_7 = '1' then
Led_7 <= '1';
end if;
end process;
You could also note that the if elsif will evaluate switches in a particular order and only take effect for the highest priority switch (first in the if then elsif then end if structure).
There aren't any ieee packages with a primary name starting with 'bit':
-- IEEE.bit_1164.ALL;
-- use IEEE.bit_ARITH.ALL;
-- use IEEE.bit_UNSIGNED.ALL;
(And you could have used std_logic).
because the mentioning of switches and LEDs you should be aware that you have only one value assigned to any of the LEDs, they will go on (the leftmost value of BIT) and when turned on, stay on if successfully synthesized and implemented in an FPGA.
Led_0 <= Switch_0; -- as a concurrent signal assignment statement.
One easy way to get rid of this phenomenon would be to not use if statements, where the LED value is related directly to switch value. Should you not want to infer simply wires joining ports you could use an else for each if statement, inside the process.
if Switch_0 = '1' then
Led_0 <= '1';
else
Led_0 <= '0';
end if;
Then there's the concurrent signal assignment statement equivalent of an if statement in a place suitable for a concurrent statement (not inside a process statement):
Led_0 <= '1' when Switch_0 = '1' else '0';
These statements would be independent or concurrent.

Answer 2

Besides David's comprehensive answer, I though I should add that VHDL has a great support for array types, and knowing how to use them is fundamental to writing more compact code.
A one-dimensional array of bits is called a bit_vector. Because you can assign to all the values in a bit_vector at once, your code could be made much more simple:
entity switches_to_leds is
port (
switches: in bit_vector(7 downto 0);
leds: out bit_vector(7 downto 0)
);
end;
architecture behavior of switches_to_leds is
begin
leds <= switches;
end;
Also take a look at the types std_logic and std_logic_vector, which are the industry standard for interfacing between digital circuits.