I am getting a warning when i try synthesize,implement, and generate program file from my VHDL Code.
When i try to synthesize i get this error
WARNING:Xst:647 - Input <BTN_3> is never used.
This port will be preserved and left unconnected if it
belongs to a top-level block or it belongs to a sub-block and
the hierarchy of this sub-block is preserved.
When i Implement it i get this
WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. The signal
does not drive any load pins in the design.
WARNING:Par:288 - The signal BTN_3_IBUF has no load.
PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design.
This design will cause Bitgen to issue DRC warnings.
and when i generate program file i get this error
WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete.
The signal does not drive any load pins in the design.
What could cause this error..
The code can be found here [http://pastebin.com/eK05tyEb][1]
[1]: http://pastebin.com/eK05tyEb - link to the code
User constrain file /.Ucf
NET "Switch_0" LOC = "G18";
NET "Switch_1" LOC = "H18";
NET "Switch_2" LOC = "K18";
NET "Switch_3" LOC = "K17";
NET "Switch_4" LOC = "L14";
NET "Switch_5" LOC = "L13";
NET "Switch_6" LOC = "N17";
NET "Switch_7" LOC = "R17";
NET "LED_0" LOC = "J14";
NET "LED_1" LOC = "J15";
NET "LED_2" LOC = "K15";
NET "LED_3" LOC = "K14";
NET "LED_4" LOC = "E17";
NET "LED_5" LOC = "P15";
NET "LED_6" LOC = "F4";
NET "LED_7" LOC = "R4";
NET "BTN_3" LOC = "H13";
Your code as you have posted may not tell the entire story. Normally there is an interface (user constraints, thanks Bob) file that defines pin edge inputs and outputs to a port of a circuit internal to the FPGA you define. I am not seeing that.
Secondly, I also see in your code that you have 2 differing circuits driving each one of your output LEDs.
You have an if statement that checks for BTN_3 being 1, which will drive ALL of the LEDs to 0, then a set of If statements checking the input state of each "Switch_X" which individually drives a 0 or one to each LED. This is actually illegal. You can only have one circuit driving any output port.
What you should do is write this circuit as follows:
architecture Behavioral of Switch_led is
begin
Process(Switch_0, Switch_1, Switch_2, Switch_3, Switch_4, Switch_5, Switch_6 , Switch_7, BTN_3)
begin
if BTN_3 = '1' then
Led_0 <= '0';
Led_1 <= '0';
Led_2 <= '0';
Led_3 <= '0';
Led_4 <= '0';
Led_5 <= '0';
Led_6 <= '0';
Led_7 <= '0';
else
if Switch_0 = '1' then
Led_0 <= '1';
else
Led_0 <= '0';
end if;
if Switch_1 = '1' then
Led_1 <= '1';
else
Led_1 <= '0';
end if;
if Switch_2 = '1' then
Led_2 <= '1';
else
Led_2 <= '0';
end if;
if Switch_3 = '1' then
Led_3 <= '1';
else
Led_3 <= '0';
end if;
if Switch_4 = '1' then
Led_4 <= '1';
else
Led_4 <= '0';
end if;
if Switch_4 = '1' then
Led_4 <= '1';
else
Led_4 <= '0';
end if;
if Switch_5 = '1' then
Led_5 <= '1';
else
Led_5 <= '0';
end if;
if Switch_6 = '1' then
Led_6 <= '1';
else
Led_6 <= '0';
end if;
if Switch_7 = '1' then
Led_7 <= '1';
else
Led_7 <= '0';
end if;
end if;
end process;
end Behavioral;
What I have essentially done is to bring all of your individual Switch_X checking into the else clause of the btn_3 check. This forces what I was stating before, that only one logic circuit will drive any LED at any point in time.
Related
I have a problem with verilog if-else statement. I'm trying to make a digital clock and my tick_counter module code like this. I pointed to error line with comment line. I cant find the solve, please help me.
module tick_counter(
input clk,
input tick_in,
output [3:0] ssd_2, ssd_4,
output [2:0] ssd_3
);
reg [5:0] count1, count_next1;
reg [2:0] count2, count_next2;
reg [3:0] count3, count4, count_next3, count_next4;
always#(posedge clk)
begin
count1 <= count_next1;
count2 <= count_next2;
count3 <= count_next3;
count4 <= count_next4;
end
//next state logic
always#*
begin
if(tick_in)
begin
if(count1==6'b111100) //second counter
begin
count_next1 = 6'b0;
count_next2 = count2 + 1'b1;
end
else
count_next1 = count1 + 1'b1;
if(count2==4'b1001) //minutes counter of LSB digit
begin
count_next2 = 4'b0000;
count_next3 = count3 + 1'b1;
end
else
count_next2 = count2 + 1'b1;
if(count3==3'b101) //minutes counter of MSB digit
begin
count_next3 = 3'b000;
count_next4 = count4 + 1'b1;
end
else
count_next3 = count3 + 1'b1;
if(count4==4'b1001) //counter hour
begin
count_next4 = 4'b0000;
end
else
count_next4 = count4 + 1'b1;
else //---THE POINT OF ERROR------
begin
count_next1 = count1;
count_next2 = count2;
count_next3 = count3;
count_next4 = count4;
end
end
end
assign ssd_2 = count2;
assign ssd_3 = count3;
assign ssd_4 = count4;
endmodule
Of course endmodule is missing. But this may be your typo mistake.
Proper indentation is greatly encouraged for large designs. Here, after indenting your code, I came to know that one end after the else part of // counter hour condition is missing. So, your main if condition's end is mis-placed. Just add end at the specified position and remove one end from the last of always block.
Kindly do proper indentation so that it becomes easy to debug.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port (sel: in std_logic;
s0,s1: in std_logic_vector (3 downto 0) ;
sout : out std_logic_vector (3 downto 0));
end mux;
architecture Behavioral of mux is
begin
if sel = '0' then
sout <= s0;
else
sout <= s1;
end if;
end Behavioral;
-- I'm Trying to make a mux for a four bit serial adder output. If the cin is 0 then it will take the
-- sum from the first adder which has cin 0 and if cin is 1 then it will take the sum from the second -- adder which i've fed with cin 1. However there is an error with the if somewhere I can't figure --out. the compiler says error near if else and end if statement
Use the if-else construct within a process with the proper sensitivity list.
`
process(sel)
begin
(
if sel = '0' then
sout <= s0;
else
sout <= s1;
end if;
);
end process;
else use theWhen Else construct
The if is a sequential statement, so it only goes inside a process. Replace if with when, since that is a concurrent statement thus can be used directly in the architecture:
sout <= s0 when (sel = '0') else s1;
I am trying to learn VHDL, and it is not going that well..
I wrote this piece of code,
library IEEE;
use IEEE.bit_1164.ALL;
use IEEE.bit_ARITH.ALL;
use IEEE.bit_UNSIGNED.ALL;
entity Switch_led is
port(
Switch_0: in bit;
Switch_1: in bit;
Switch_2: in bit;
Switch_3: in bit;
Switch_4: in bit;
Switch_5: in bit;
Switch_6: in bit;
Switch_7: in bit;
Led_0: out bit;
Led_1: out bit;
Led_2: out bit;
Led_3: out bit;
Led_4: out bit;
Led_5: out bit;
Led_6: out bit;
Led_7: out bit
);
end Switch_led;
architecture Behavioral of Switch_led is
begin
if Switch_0 = '1' then
Led_0 <= 1;
elsif Switch_1 = '1' then
Led_1 <= 1;
elsif Switch_2 = '1' then
Led_2 <= 1;
elsif Switch_3 = '1' then
Led_3 <= 1;
elsif Switch_4 = '1' then
Led_4 <= 1;
elsif Switch_5 = '1' then
Led_5 <= 1;
elsif Switch_6 = '1' then
Led_6 <= 1;
elsif Switch_7 = '1' then
Led_7 <= 1;
end if;
end Behavioral;
For some reason i get errors to my if statements in my architecture. But I aren't able to find what the mistake is. I hope the code makes sense.
The enumeration names for type bit are given in package standard.
type BIT is ('0', '1');
These sort of assignments:
Led_0 <= 1;
Should look like:
Led_0 <= '1';
You'll also note that an if statement is used in a place suitable for a sequential statement, meaning all those should be in a process statement.
SWITCH:
process (Switch_0,Switch_1,Switch_2,Switch_3,Switch_4,Switch_5, Switch_6,Switch_7)
begin
if Switch_0 = '1' then
Led_0 <= '1';
elsif Switch_1 = '1' then
Led_1 <= '1';
elsif Switch_2 = '1' then
Led_2 <= '1';
elsif Switch_3 = '1' then
Led_3 <= '1';
elsif Switch_4 = '1' then
Led_4 <= '1';
elsif Switch_5 = '1' then
Led_5 <= '1';
elsif Switch_6 = '1' then
Led_6 <= '1';
elsif Switch_7 = '1' then
Led_7 <= '1';
end if;
end process;
You could also note that the if elsif will evaluate switches in a particular order and only take effect for the highest priority switch (first in the if then elsif then end if structure).
There aren't any ieee packages with a primary name starting with 'bit':
-- IEEE.bit_1164.ALL;
-- use IEEE.bit_ARITH.ALL;
-- use IEEE.bit_UNSIGNED.ALL;
(And you could have used std_logic).
because the mentioning of switches and LEDs you should be aware that you have only one value assigned to any of the LEDs, they will go on (the leftmost value of BIT) and when turned on, stay on if successfully synthesized and implemented in an FPGA.
Led_0 <= Switch_0; -- as a concurrent signal assignment statement.
One easy way to get rid of this phenomenon would be to not use if statements, where the LED value is related directly to switch value. Should you not want to infer simply wires joining ports you could use an else for each if statement, inside the process.
if Switch_0 = '1' then
Led_0 <= '1';
else
Led_0 <= '0';
end if;
Then there's the concurrent signal assignment statement equivalent of an if statement in a place suitable for a concurrent statement (not inside a process statement):
Led_0 <= '1' when Switch_0 = '1' else '0';
These statements would be independent or concurrent.
Besides David's comprehensive answer, I though I should add that VHDL has a great support for array types, and knowing how to use them is fundamental to writing more compact code.
A one-dimensional array of bits is called a bit_vector. Because you can assign to all the values in a bit_vector at once, your code could be made much more simple:
entity switches_to_leds is
port (
switches: in bit_vector(7 downto 0);
leds: out bit_vector(7 downto 0)
);
end;
architecture behavior of switches_to_leds is
begin
leds <= switches;
end;
Also take a look at the types std_logic and std_logic_vector, which are the industry standard for interfacing between digital circuits.
Hello friends and pro programmers, im new to this world of VHDL and i have this question.
i want to make this:
if counter >= 0 and counter <=95 then
aux_Hs <= '0';
else
aux_Hx <= '1';
end if;
in something like this:
aux_Hs <= (counter >= 0 and counter <=95);
this error shows up:
Line 73. Type of aux_Hs is incompatible with type of and.
aux_Hs is a signal STD_Logic.
is there some way to save the IF statements? a pseudo " ? : " instruction?.
Thank you in advance :)
As concurrent code, without VHDL-2008:
aux_Hs <= '1' when (counter >= 0 and counter <=95) else '0' ;
With VHDL-2008:
aux_Hs <= counter ?>= 0 and counter ?<=95 ;
If you need to do this inside a process, you can save a line of code like this:
aux_Hs <= '0';
if not (counter >= 0 and counter <=95) then
aux_Hx <= '1';
end if;
Or you can use VHDL-2008 (look for the switches on your compiler and log a bug if VHDL2008 is not supported!) which allows conditional assigment inside processes:
aux_Hs <= '0' when (counter >= 0 and counter <=95) else '1' ;
I am writing code for comparing a signal to a number of signals at the same time.
Here is the example:
process (CLK, reset)
if reset = '0' then
data <= (others => '0');
elsif rising_edge (CLK) then
if A = B then
data <= data OR "0001";
else data <= data AND "1110";
end if;
if A = C then
data <= data OR "0010";
else data <= data AND "1101";
end if;
if A = D then
data <= data OR "0100";
else data <= data AND "1011";
end if;
if A = E then
data <= data OR "1000";
else data <= data AND "0111";
end if;
end if;
end process;
I just want to comparing the A to B, C, D and E signals and then turn the associated bits in data on and off. The code I wrote above is not working since the synthesis tool will optimize the B, C and D if statements and only leaving the E if statement. I have also thought about using case - when statement but it doesn't have a mechanism to turn off the associated single bit off. When others can only turn all 4 bits off. What is the effective way to do this? Thanks!
BTW, are all these 4 if statements run at the same time? Or they are run at different cycles? I guess they would run one by one, otherwise it would cause fan-in.
You are trying to write C in a language where you don't have to!
In C you can't access a single bit, only bytes and larger units so C programmers have to resort to AND/OR i.e. &,| to set or clear bits.
In VHDL you can address individual bits of a word, and write
if A = B then
data(0) <= '1';
else
data(0) <= '0';
end if;
Much simpler. And yes they all run at the same time, every clock cycle.
I would prefer to declare data as an array of booleans,
signal data : array(3 downto 0) of boolean;
Then I could write
process (CLK, reset)
begin
if reset = '0' then
data <= (others => false);
elsif rising_edge (CLK) then
data <= (A = E) & (A = D) & (A = C) & (A = B);
end if;
end process;
If I had to use a std_logic_vector for data, the convenience of this form is (almost) tempting enough to make me overload the "=" operator for A's type with one returning std_logic.
Then, for the price of writing a tiny function, I could keep this code.
EDIT:
To address the reason the original approach doesn't work, it is necessary to understand the semantics of signal assignment, as explained for example here.
So the first assignment to Data (for A=B) is stored up to happen after the process suspends. Then the second assignment replaces it BEFORE IT HAPPENED so the first such assignment never takes place.
What you need for the original approach to work, is a variable because variable assignments happen immediately.
process (CLK, reset)
variable data_int : whatever; -- same type as data
begin
if reset = '0' then
data <= (others => '0');
elsif rising_edge (CLK) then
data_int := data;
if A = B then
data_int := data_int OR "0001";
else data_int := data_int AND "1110";
end if;
...
if A = E then
data_int := data_int OR "1000";
else data_int := data_int AND "0111";
end if;
data <= data_int;
end if;
end process;
Now the single assignment to data will contain all the separate modifications. However it might synthesise to something much larger than the optimal solutions.