I am trying to compile a program consisting of two source files:
wildcardtrie.h, wildcardtrie.cpp
using a Makefile. However, when I run GDB to debug, I get the following error:
Reading symbols from /home/meric/Documents/Random/SectionLeading/wildcardtrie...(no debugging symbols found)...done.
I have tried a number of different compiler flags, none of which worked. The thing that perplexes me is that I have used a nearly identical Makefile in other programs and missing symbols has never been a problem. I have included the Makefile below:
CC=g++
CFLAGS = -g -ggdb g++ -O0 -Wall -Wfloat-equal -Wtype-limits -Wpointer-arith -Wlogical- op -fno-diagnostics-show-option
LDFLAGS = -g -ggdb -std=c++0x
programs = wildcardtrie
all : $(programs)
clean:
rm -f $(programs) core *.o
.PHONY: clean all
I have tried removing '-g' and '-ggdb' in the compiler and linker flags, but nothing seems to work. When I call 'make', I get the following output on the terminal:
g++ -c -o wildcardtrie.o wildcardtrie.cpp
g++ -g -ggdb -std=c++0x wildcardtrie.o -o wildcardtrie
Any help would be greatly appreciated!
g++ -c -o wildcardtrie.o wildcardtrie.cpp
This clearly shows that -g is not on your compile line (which is exactly the cause of your problem).
To get -g there, either add it to CXXFLAGS (this is the preferred solution), or just write the compile rule explicitly (instead of relying on built-in make rule):
wildcardtrie.o: wildcardtrie.cpp
$(CC) $(CFLAGS) -o wildcardtrie.o wildcardtrie.cpp
Related
I need help configuring my makefile to use it with the GNU debugger. I am running it on debian.
I am quite new to makefiles and after going through similar questions I've tried adapting the answers of those to my code, but it didn't work out the ways I tried (probably because i don't fully understand the syntax of makefiles).
This is the original (shortened) makefile:
INC=-I include
all: libs poisson_solver
poisson_solver:
g++ -o bin/poisson $(INC) src/main.c\ src/problem_setup.c\ libs/timer_tools.o
libs: libs/timer_tools.o src/problem_setup.o
libs/timer_tools.o: utilities/gettime.c
g++ -c -o libs/timer_tools.o $(INC) utilities/gettime.c
src/problem_setup.o: src/problem_setup.c include/problem_setup.h
g++ -c -o src/problem_setup.o $(INC) src/problem_setup.c include/problem_setup.h
Your Makefile has several errors, and in general contains more cruft than it should.
Here is roughly what it should be:
CFLAGS = -Iinclude -g
OBJS = src/main.o src/problem_setup.o utilities/gettime.o
all: poisson_solver
poisson_solver: $(OBJS)
src/problem_setup.o: src/problem_setup.c include/problem_setup.h
See this section of the manual.
For a project, I have to create a simple makefile for the source code which includes pthreads and command line arguments (if those matter to include).
The first version of the makefile that didn't work was this:
mr: mr.o
g++ -std=c++11 -pthread mr.o -o mr
mr.o: mapred.cc
g++ -std=c++11 -pthread -c mapred.cc
clean:
rm *.o mr
and I got the following error that the object file did not exist?
So then I decided to flip the two first statements around:
mr.o: mapred.cc
g++ -std=c++11 -pthread -c mapred.cc
mr: mr.o
g++ -std=c++11 -pthread mr.o -o mr
clean:
rm *.o mr
and it compiles, sort of? All I get in the terminal is:
g++ -std=c++11 -pthread -c mapred.cc
and nothing else. When I look at what files were created, all I see is a new file mapred.o created but no executable. So no errors but not fully completed. If you guys have any tips to help me out that would be very appreciated. Thank you!
If you don't specify an explicit output name with the -o option, then the compiler will name object file the same as the source file but with an .o suffix.
In your case, the command
g++ -std=c++11 -pthread -c mapred.cc
will create an object file named mapread.o.
Either use mapread.o for your target names and when linking, or use the -o option:
g++ -std=c++11 -pthread -c mapred.cc -o mr.o
As for your second problem, unless you specify an explicit target when invoking make, it will only use the first target and nothing else.
I'm trying to run a simple makefile that looks like this:
T=-ansi -pedantic -Wall -Werror
a.out: test.o extra.o
gcc $(T) -c test.o extra.o
test.o: test.c test.h
gcc $(T) -c test.c
extra.o: extra.c extra.h
gcc $(T) -c extra.c
clean:
rm *.o a.out
But I seem to be getting warnings telling me that "linker input file unused because linking not done"
I tried removing the "-c" from the a.out directive, after the gcc, but that produced to give me more problems. I'm not sure how to go about proceeding from here, any ideas/input would be much appreciated.
EDIT: I'm running the program by "make -T", also removing the -c from a.out, causes the error" invalid symbol index"
You need to remove the -c from the a.out command:
a.out: test.o extra.o
gcc $(T) test.o extra.o
or, better:
a.out: test.o extra.o
gcc $(T) -o $# test.o extra.o
or, still better:
extra: test.o extra.o
gcc $(T) -o $# test.o extra.o
The error message is normally because you specify something like -lm on a command line with -c, but you're not doing that here. OTOH, you are listing object files with the -c option — that'll generate the warning:
gcc -ansi -pedantic -Wall -Werror -c test.o extra.o
^ this one, here
Those .o files are the linker inputs, but you're not linking. Drop the -c and you will generate a.out. That should proceed OK.
I think this is the first time I've seen a makefile used to build a.out. It is unusual in the extreme — not precisely wrong, but definitely not the way you normally use make. It has built-in rules to build programs from single source files, such as example from example.c. Normally, you give a program a meaningful name based on one of the source files. Note that creating a program test is usually a bad idea; there is a standard test command built into the typical shell and confusion is rampant.
I have made a Makefile for my CMSC 202 course project, 'Blackjack'. It does everything I need it to and it works perfectly. You may be asking why I posted here then, this is because I have no idea how it works and I didn't use any other resources but myself to create it.
Here is my Makefile code.
# Object files to either reference or create
OBJECTS = Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
# The executable file that will be created at the end
EXEC = Proj2.out
# The flags to use for compilation
FLAGS = -Wall
# The code compiler to use for compilation
CC = g++
# Perform action on all object files (May or may not exist)
all: $(OBJECTS)
$(CC) $(FLAGS) -o $(EXEC) $(OBJECTS)
Here is the terminal output when I call make in the terminal.
g++ -c -o Proj2.o Proj2.cpp
g++ -c -o Blackjack.o Blackjack.cpp
g++ -c -o Deck.o Deck.cpp
g++ -c -o Card.o Card.cpp
g++ -c -o Hand.o Hand.cpp
g++ -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Can anyone tell me how the .o files are being compiled? It does not look like they are being prompted to be compiled with that g++ -c -o $.o $.cpp command anywhere in the Makefile. Nor did I state to use any .cpp files.
Thank you in advance for your help.
Edit
Thanks to all your great help, this is now the terminal output I receive when using make.
g++ -Wall -c -o Proj2.o Proj2.cpp
g++ -Wall -c -o Blackjack.o Blackjack.cpp
g++ -Wall -c -o Deck.o Deck.cpp
g++ -Wall -c -o Card.o Card.cpp
g++ -Wall -c -o Hand.o Hand.cpp
g++ -Wall -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Thank you so much to all of you who have contributed.
Make has a set of implicit rules (see here for a reference). For instance
Compiling C++ programs
`n.o' is made automatically from `n.cc' or `n.C' with a command of the form
`$(CXX) -c $(CPPFLAGS) $(CXXFLAGS)'.
Most make's will also use this rule for .cpp files.
When make sees there's a x.o requirement for one of your targets, it will try to see if it can generate x.o using implicit rules, and in your case find it can do it starting from a .cpp file.
This Makefile uses implicit rules which are a great way to reduce duplication.
By default the first target will be built, here all. It depends on a number
of object files listed in a variable $OBJECTS, e.g. Proj2.o who's
dependencies aren't listed in the Makefile. Now if make sees an input file in the current directory
with a matching name, e.g. Proj2.cpp it will try
to build Proj2.o from it (there are other implicit rules for sources in
other languages). Proj2.o would then be built by default with the command
$(CXX) $(CXXFLAGS) -c -o Proj2.o
where $(CXX) the name of the C++ compiler (g++ in your case).
The explicit build step for all assembles all the object files into the
target executable.
Looking at above build command you'll notice a small problem in your Makefile. Since the flags to the C++ compiler are given in a variable FLAGS and not the standard CXXFLAGS no warnings will be emitted when building the object files. Using the standard name would fix this (you do want warnings, maybe even more than -Wall gives you).
I'm building a package which provides many makefiles, each makefile has hard coded in side something like
CFLAGS = -g -O2 -Wall ...
CXXFLAGS = -g -O2 -Wall ...
I want to discard -g option but I don't want to edit all makefiles (even not automatically with sed or something similar). The configure script which comes with the package doesn't have enable/disable debug option but I can pass it CFLAGS and CXXFLAGS variables and it concatenates their values to the CFLAGS and CXXFLAGS variables respectively which include the -g option.
Is there an option which will discard -g in case it is specified? Something like
gcc -option-im-looking-for -g file.c -o file
Will build the binary file without debug symbols. I don't want to strip the binary, I want it to be created stripped.
You could negate the effect of -g by adding -g0. Saying
gcc -g -g0 foo.c -o file.o
would produce a binary identical to one obtained by saying
gcc foo.c -o foo.o
Quoting man gcc:
-glevel
...
Level 0 produces no debug information at all. Thus, -g0 negates
-g.
You don't need to edit makefiles. Just override the variables on the command line:
$ cat Makefile
CFLAGS = -g -Wall
all:
echo $(CFLAGS)
$ make
echo -g -Wall
-g -Wall
$ make CFLAGS=-Wall
echo -Wall
-Wall