I want to use scons for the building process of a small game I wrote. https://github.com/Dobiasd/Dron
I generally works including the recursion through the source directories, but I would like to not pollute src directory with .o files. VariantDir should help me, but the following SConstruct does not work (.o files still in ./src)
import fnmatch
import os
matches = []
for root, dirnames, filenames in os.walk('src/'):
for filename in filenames:
if fnmatch.fnmatch(filename, '*.cpp'):
matches.append(str(os.path.join(root, filename)))
env = Environment()
env.Append(LIBS = ['sfml-audio', 'sfml-graphics','sfml-window','sfml-system'])
env.Append(LIBPATH = '/usr/local/lib')
env.Append(CXXFLAGS = '-std=c++11 -Wall -Wextra -pedantic -Werror')
env.VariantDir('build', 'src')
env.Program(target = 'Dron', source = matches)
compilation (my expectation):
g++ -o obj/main.o -c -std=c++11 -Wall -Wextra -pedantic -Werror src/main.cpp
compilation (reality):
g++ -o src/main.o -c -std=c++11 -Wall -Wextra -pedantic -Werror src/main.cpp
It would be great if someone could tell me what I am doing wrong. :)
When using the SCons VariantDir() function, you have to refer to your source files as if they were in the variant_dir, not the source_dir.
Here is an answer to a different question, that should serve as a good example and should help.
Related
I was building some Cython extensions, and have to link it against a static library (it has CUDA code in them, so have to be static):
running build_ext
building 'k3lib' extension
gcc -pthread -B /home/kelvin/anaconda3/envs/torch/compiler_compat -Wl,--sysroot=/ -Wsign-compare -DNDEBUG -g -fwrapv -O3 -Wall -Wstrict-prototypes -fPIC -I/home/kelvin/repos/tools/include -I/home/kelvin/anaconda3/envs/torch/include/python3.8 -c main.cpp -o build/temp.linux-x86_64-3.8/main.o -O3 -march=native
cc1plus: warning: command line option ‘-Wstrict-prototypes’ is valid for C/ObjC but not for C++
g++ -pthread -shared -B /home/kelvin/anaconda3/envs/torch/compiler_compat -L/home/kelvin/anaconda3/envs/torch/lib -Wl,-rpath=/home/kelvin/anaconda3/envs/torch/lib -Wl,--no-as-needed -Wl,--sysroot=/ build/temp.linux-x86_64-3.8/main.o /home/kelvin/repos/tools/include/libk2.a -L/home/kelvin/repos/tools/include -lk2 -o build/lib.linux-x86_64-3.8/k3lib.cpython-38-x86_64-linux-gnu.so -static -Wl,-Bstatic -flinker-output=exec
However, Cython's g++ compile command includes the options -shared -fPIC by default. I tried a number of options at the end of the command via this setup file (the static library is at $(LOCAL_INCLUDE)/libk2.a):
includes = [os.getenv("LOCAL_INCLUDE")]
ext_modules = [
Extension("k3lib", sources=["main.pyx"],
libraries=["k2"], include_dirs=includes, library_dirs=includes, language="c++",
extra_compile_args=["-O3", "-march=native"], extra_objects=[f"{includes[0]}/libk2.a"],
extra_link_args=['-static', '-Wl,-Bstatic', '-flinker-output=exec'])
]
#extra_objects=[f"{includes[0]}/libk2.a"]
#extra_link_args=['-static']
setup(name="k3lib", ext_modules=cythonize(ext_modules, language_level="3"))
Still, g++ thinks that I want to build a shared library, and thus the error message. Is there a way to override the -shared option? I'm planning to go into Cython's files and edit them myself, but was wondering is there a simpler way?
Context: I was following this question on SO but can't replicate their success.
I can't seem to include a header in my test program using a Makefile.
I've attempted to try relative paths using -I with no luck. I'm new to Make and for some reason I am having a hard time understanding it's usage.
my code, test.cpp
#include <iostream>
#include <results/enumTest.h>
int main()
{
return 0;
}
and my Makefile:
CFLAGS = -Wall -g -Wextra -Wpedantic -std=gnu++11 -m64 -Iinclude
test: test.o
gcc $(CFLAGS) -I/.. -o test test.o
test.o: test.cpp
gcc $(CFLAGS) -I/.. -c test.cpp
my directory structure:
/testDir/
./results/enuMtest.h
./test/test.cpp
./test/Makefile
I would hope that I could compile and then run the test software using a Makefile. This is more or less a tutorial for me.
Your include path -I/.. is invalid. You're trying to access the parent directory of the root directory, which cannot exist. Change your Makefile to use relative paths instead with -I..
This will access the parent directory as intended:
CFLAGS = -Wall -g -Wextra -Wpedantic -std=gnu++11 -m64 -Iinclude
test: test.o
g++ $(CFLAGS) -I.. -o test test.o # Change here
test.o: test.cpp
g++ $(CFLAGS) -I.. -c test.cpp # ...and here
Note the removed slashes.
EDIT: As commented by #Lightness, you should include non-system headers with "header.h" rather than <header.h>. Additionally, since you are trying to compile a C++ program, it is recommended to use g++ instead of gcc (I've updated this in the snippet above).
There are several improvements possible.
You try to set the include path to the parent dir of / which is /.
You try to compile a c++ program using gcc but not g++
You don't need (it would still work) to set an include path, when linking. (test:
test.o)
Since there is no directory named include in the filetree you specified, you also don't need -Iinclude in the CFLAGS
Usually the C++ variant of CFLAGS is named CXXFLAGS, but I did not change it in the modified example below.
A corrected makefile would be:
CFLAGS = -Wall -g -Wextra -Wpedantic -std=gnu++11 -m64
test: test.o
g++ $(CFLAGS) -o test test.o
test.o: test.cpp
g++ $(CFLAGS) -I.. -c test.cpp
As an additional note:
#include "" instead of #include <> would also work. The difference is, that "" searches the included file relative from the location of the current source file, while <> uses the directories you specify using -I.
Find more details here
I am having difficulty trying to create a makefile that is in a root directory which will then CD into another directory entitled "code" which is where my code will be compiled. Also the executable then needs to be placed in a new directory which will be created called "bin" which will be in the root directory I have this so far:
all: bin/main
test: bin/main
bin/main: main.cpp
mkdir -p bin
g++ -std=c++11 -Wall -Werror -ansi -pedantic -o bin/program main.cpp
NOTE: I need those two target all and test. However this make (above) will only work if my code is already in the root
UPDATE: renamed code directory to src and here is new makefile
all:
mkdir -p ./bin
g++ -std=c++11 -Wall -Werror -ansi -pedantic ./src/main.cpp -o./bin/prgm
test:
mkdir -p ./bin
g++ -std=c++11 -Wall -Werror -ansi -pedantic ./src/main.cpp -o ./bin/prgm
however now I get this error "make: *** makefile: Is a directory. Stop."
Am I trying to run it right? I do this "$ make"
Here is simplest take, You can do many more things like making the target all phoney etc to keep it simple for demonstration.
all:
- mkdir -p bin
g++ -std=c++11 -Wall -Werror -ansi -pedantic -o bin/program src/main.cpp
Hope, you can figure out for target test.
I am trying to compile a program consisting of two source files:
wildcardtrie.h, wildcardtrie.cpp
using a Makefile. However, when I run GDB to debug, I get the following error:
Reading symbols from /home/meric/Documents/Random/SectionLeading/wildcardtrie...(no debugging symbols found)...done.
I have tried a number of different compiler flags, none of which worked. The thing that perplexes me is that I have used a nearly identical Makefile in other programs and missing symbols has never been a problem. I have included the Makefile below:
CC=g++
CFLAGS = -g -ggdb g++ -O0 -Wall -Wfloat-equal -Wtype-limits -Wpointer-arith -Wlogical- op -fno-diagnostics-show-option
LDFLAGS = -g -ggdb -std=c++0x
programs = wildcardtrie
all : $(programs)
clean:
rm -f $(programs) core *.o
.PHONY: clean all
I have tried removing '-g' and '-ggdb' in the compiler and linker flags, but nothing seems to work. When I call 'make', I get the following output on the terminal:
g++ -c -o wildcardtrie.o wildcardtrie.cpp
g++ -g -ggdb -std=c++0x wildcardtrie.o -o wildcardtrie
Any help would be greatly appreciated!
g++ -c -o wildcardtrie.o wildcardtrie.cpp
This clearly shows that -g is not on your compile line (which is exactly the cause of your problem).
To get -g there, either add it to CXXFLAGS (this is the preferred solution), or just write the compile rule explicitly (instead of relying on built-in make rule):
wildcardtrie.o: wildcardtrie.cpp
$(CC) $(CFLAGS) -o wildcardtrie.o wildcardtrie.cpp
I'm building a package which provides many makefiles, each makefile has hard coded in side something like
CFLAGS = -g -O2 -Wall ...
CXXFLAGS = -g -O2 -Wall ...
I want to discard -g option but I don't want to edit all makefiles (even not automatically with sed or something similar). The configure script which comes with the package doesn't have enable/disable debug option but I can pass it CFLAGS and CXXFLAGS variables and it concatenates their values to the CFLAGS and CXXFLAGS variables respectively which include the -g option.
Is there an option which will discard -g in case it is specified? Something like
gcc -option-im-looking-for -g file.c -o file
Will build the binary file without debug symbols. I don't want to strip the binary, I want it to be created stripped.
You could negate the effect of -g by adding -g0. Saying
gcc -g -g0 foo.c -o file.o
would produce a binary identical to one obtained by saying
gcc foo.c -o foo.o
Quoting man gcc:
-glevel
...
Level 0 produces no debug information at all. Thus, -g0 negates
-g.
You don't need to edit makefiles. Just override the variables on the command line:
$ cat Makefile
CFLAGS = -g -Wall
all:
echo $(CFLAGS)
$ make
echo -g -Wall
-g -Wall
$ make CFLAGS=-Wall
echo -Wall
-Wall