can compiler options be applied selectively on my files?
I want some files to be covered by some option but not the other files.
Guessing that you might be using Make files:
This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1.exe
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2
Of course. You invoke the compiler, and you can tell it what you want.
Some tools may add some restrictions; Visual Studio, as far as I know, only allows specifying options at the project level. But that's an artificial restriction of the tool (and I'm sure there are ways around it—I just don't know them).
Related
I have a makefile as follows:
# Makefile for VocabLearn
MACHTYPE=$(shell uname -m)
GCC = g++
CC=gcc
# OPTFLAGS=-g2
OPTFLAGS=-O3 -ffast-math -Wall -mfpmath=sse -msse2 -funroll-loops -march=core2
OTHERFLAGS=-Wall -fopenmp
INCLUDE_PATH=-I../lib/ann_1.1/include/ANN -I../lib/ann_1.1_char/include/ANN \
-I../lib/imagelib -I../VocabLib -I../lib/zlib/include
LIB_PATH=-L../lib -L../VocabLib -L../lib/zlib/lib
OBJS=VocabLearn.o
LIBS=-lvocab -lANN -lANN_char -limage -lz
CPPFLAGS=$(INCLUDE_PATH) $(LIB_PATH) $(OTHERFLAGS) $(OPTFLAGS)
BIN=VocabLearn
all: $(BIN)
$(BIN): $(OBJS)
g++ -o $(CPPFLAGS) -o $(BIN) $(OBJS) $(LIBS)
clean:
rm -f *.o *~ $(LIB)
When I 'make' it in the prompt, it works fine and output the following info:(I use Mac OS, c++ means clang compiler)
c++ -I../lib/ann_1.1/include/ANN -I../lib/ann_1.1_char/include/ANN
-I../lib/imagelib -I../VocabLib -I../lib/zlib/include -L../lib -L../VocabLib -L../lib/zlib/lib -Wall -fopenmp -O3 -ffast-math -Wall -mfpmath=sse -msse2 -funroll-loops -march=core2 -c -o VocabLearn.o VocabLearn.cpp
g++ -o -I../lib/ann_1.1/include/ANN -I../lib/ann_1.1_char/include/ANN
-I../lib/imagelib -I../VocabLib -I../lib/zlib/include -L../lib -L../VocabLib -L../lib/zlib/lib -Wall -fopenmp -O3 -ffast-math -Wall -mfpmath=sse -msse2 -funroll-loops -march=core2 -o VocabLearn VocabLearn.o -lvocab -lANN -lANN_char -limage -lz
I just want to know how this makefile works. As you can see, since this makefile doesn't specify which source code to compile, how does the compiler know it is 'VocabLearn.cpp' that it should process? (My guess is that it will search source file according to the name of the object file, VocabLearn.o) Also this line seems a bit strange for me:
g++ -o $(CPPFLAGS) -o $(BIN) $(OBJS) $(LIBS)
Why is there a '-o' before '$(CPPFLAGS)'?
This makefile is using implicit rules to compile the source files. The rule:
$(BIN): $(OBJS)
asks for the object files in OBJS, and make already knows how to build VocabLearn.o if there is a file VocabLean.cpp.
Basically there is an implicit rule to convert *.cpp files to *.o files, however you have to have *.o as a dependency in one your targets. In the given Makefile, you have VocabLearn.o as a dependency for $(BIN). So, VocabLearn.o gets auto-generated from VocabLearn.cpp file.
I have created a small library (around 600 lines) in C++ in Codeblocks and I'm using OMP and O3 optimization to build it. When I try to build the same code through the terminal with a Makefile with exactly the same options (-fopenmp -O3) it runs around 3 times slower. I need to build it in various machines so I need to do the process through a terminal and not through Codeblocks. Why is this happening?
This is my Makefile if you're interested:
CC=g++
CFLAGS=
LDFLAGS= -fopenmp -O3 -std=c++11
SOURCES=main.cpp CNNFunctions.cpp
OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=cnn
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
.cpp.o:
$(CC) $(CFLAGS) $< -o $#
Your Makefile is wrong. The optimization flags are relevant mostly at compile time. Try at least:
CXX=g++
CXXFLAGS= -Wall -fopenmp -O3 -std=c++11 -mtune=native
LDFLAGS= -fopenmp
SOURCES=main.cpp CNNFunctions.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=cnn
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(LINK.cpp) $(OBJECTS) -o $#
Optimization might matter at link time for Link-Time Optimization, for that use CXX=g++ -flto and LDFLAGS=$(CXXFLAGS)
Because, contrary to your claim, you're not building it with the exact same options.
Your CFLAGS are empty, and those are the flags you're using for the compilation. You cannot resolve that by the time you get to the linking step.
I want to use a single make file to generate a project in multiple modes, and then each mode in a "normal" and "debug" mode, ie:
I have the following files (ofc more in reality, but this will serve to show my point):
kernel/core/main.cpp
kernel/processor/Processor.cpp
kernel/processor/x86/Processor.cpp
kernel/processor/x86_common/Processor.cpp
kernel/processor/x64/Processor.cpp
And i want to be able to use my makefile in the following ways:
make x86
(compiles all files except "kernel/processor/x64/Processor.cpp")
(enables the pre-processor directives X86 & X86_COMMON)
And,
make x86debug
(compiles all files except "kernel/processor/x64/Processor.cpp")
(enables the pre-processor directives X86 & X86_COMMON & DEBUG)
(puts "-g -ggdb" infront of all gcc/g++/as arguments)
And so on.
Currently i have the following makefile, which while it works, only lets me compile in x86-debug mode and now that i am porting my software to other platforms I wish to be able to specify what mode to build in.
CC = i586-elf-g++
CFLAGS = -g -ggdb -ffreestanding -Wall -Wextra -fno-exceptions -fno-rtti -std=gnu++11 -Isrc/system/include -DX86 -DX86_COMMON
LD = i586-elf-gcc
LDFLAGS = -g -ggdb -ffreestanding -O2 -nostdlib -lgcc
AS = i586-elf-as
ASFLAGS = -g -ggdb
OBJECTS = src/system/kernel/core/main.o
ALL_OBJECTS = $(OBJECTS) $(X86_OBJECTS)
X86COMMON_OBJECTS = src/system/kernel/core/processor/x86_common/Processor.o
X86_OBJECTS = $(X86COMMON_OBJECTS) src/system/kernel/core/processor/x86/boot.o
X86_LINKER = src/system/kernel/core/processor/x86/link.ld
X86_OUTPUT = bin/kernel_x86.bin
.PHONY: clean
clean: $(ALL_OBJECTS)
rm $(ALL_OBJECTS)
.PHONY: all
all: $(X86_OUTPUT)
$(X86_OUTPUT): $(X86_LINKER) $(OBJECTS) $(X86_OBJECTS)
$(LD) $(LDFLAGS) -T $(X86_LINKER) $^ -o $#
%.o: %.cpp
$(CC) $(CFLAGS) -c $< -o $#
%.o: %.asm
$(AS) $(ASFLAGS) $< -o $#
As you can probably tell, im not an expert with make so any help/ideas would be appreciated.
Remove -g from CFLAGS and LDFLAGS, and add the following PHONY:
.PHONY: x86_debug
x86_debug: CFLAGS += -g
x86_debug: LDFLAGS += -g
x86_debug: $(X86_OUTPUT)
To compile in normal mode: make.
To compile in debug mode: make x86_debug
It may not do exactly what you're expecting, but it's easy to modify
Here is makefile:
CC=g++
CC_FLAGS=-Wall -march=native -ffast-math -O3
CC_SOURCES=AbsNode.cpp rle16.cpp
CC_OBJECTS=AbsNode.o rle16.o
# Link command:
test : $(CC_OBJECTS)
$(CC) $(CC_OBJECTS) -o test
# Compilation commands:
%.o:%.cpp
$(CC) -c $(CC_FLAGS) $(input) -o $(output)
when applying make to this makefile, I get the following output:
g++ -c -Wall -march=native -ffast-math -O3 -o
g++: arguemnt to '-o' missing
Why are inputs and outputs ignored???
You haven't defined the variables input and output anywhere. The computer is not a magic box that can guess your intentions.
Your .cpp -> .o implicit rule is incorrect:
%.o: %.cpp
$(CC) -c $(CC_FLAGS) $< -o $#
$< is set by make to be the source file
$# will be the output file name
I have a makefile that can be reduced to this:
OBJS = obj1.o obj2.o
FLAGS = -Wall -Wextra -Werror -pedantic-errors -fno-rtti -std=c++0x
DEBUG_FLAGS = -ggdb -O0 -fstack-protector-all -D_GLIBCXX_DEBUG
RELEASE_FLAGS = -O3
release: $(OBJS)
g++ $(FLAGS) $(RELEASE_FLAGS) $(OBJS)
debug: $(OBJS)
g++ $(FLAGS) $(DEBUG_FLAGS) $(OBJS)
obj1.o: obj1.cpp
g++ -c $(FLAGS) obj1.cpp
obj2.o: obj2.cpp
g++ -c $(FLAGS) obj2.cpp
The problem is that all or none of the files must be built with the -D_GLIBCXX_DEBUG flag. I don't know how to do this without writing two entries for every compilation unit, like
obj1_release.o: obj1.cpp
g++ -c $(FLAGS) $(RELEASE_FLAGS) obj1.cpp
obj1_debug.o: obj1.cpp
g++ -c $(FLAGS) $(DEBUG_FLAGS) obj1.cpp
How can I make the -D_GLIBCXX_DEBUG flag (and the other debug flags) take effect for all compilation units only when the user types make debug without writing two entries for every CU? (And vice versa; the release flags need to take effect on all CUs when the user types make release.)
I apologise if this is the basics of writing Makefiles, I don't know much about them.
You are looking for pattern rules: something like this should do what you want. Note that this cannot be made to work correctly unless the debug and release versions of the program are given different names.
OBJS := obj1 obj2 obj3
R_OBJS := $(OBJS:=_r.o)
D_OBJS := $(OBJS:=_d.o)
all: prog_r prog_d
release: prog_r
debug: prog_d
prog_r: $(R_OBJS)
$(CXX) $(CXXFLAGS) $(RELEASE_FLAGS) $(LDFLAGS) $^ $(LIBS) -o $#
prog_d: $(D_OBJS)
$(CXX) $(CXXFLAGS) $(DEBUG_FLAGS) $(LDFLAGS) $^ $(LIBS) -o $#
%_r.o: %.cc
$(CXX) $(CXXFLAGS) $(RELEASE_FLAGS) -c $< -o $#
%_d.o: %.cc
$(CXX) $(CXXFLAGS) $(DEBUG_FLAGS) -c $< -o $#
# header files
obj1_d.o obj1_r.o: foo.h bar.h
obj2_d.o obj2_r.o: quux.h
# ... etc ...
There is a pretty straightforward way to select compilation flags based on the type of the build in Makefiles.
In addition to that you may like to ensure that debug build only links debug object files and same for release (i.e. no mixing debug and release object files). To achieve that compile object into different directories depending on the build type.
This might help : http://sunsite.ualberta.ca/Documentation/Gnu/make-3.79/html_chapter/make_7.html
You could check the first argument (debug/release) and set the CFLAGS accordingly.
HTH.