I am trying to compile my program with debugging symbols for use in gdb. I have added the -g flag to my makefile but I still get "Reading symbols from ...(no debugging symbols found)" when I load the program in gdb. What is wrong??
Here is a stripped down example of my makefile which should have the relevant bits:
CPP = g++
CFLAGS = -c -g -Wall
$(BIN): $(OBJ)
$(CPP) $(LDFLAGS) $(OBJ) -o $(BIN) $(LIBS)
<test.o>: <test.cpp>
$(CPP) $(CFLAGS) <test.cpp> -o <test.o>
If you'd like to see the whole thing you can go here instead, though I don't think it's necessary:
http://pastebin.com/vGNjy0ga
Miscellaneous notes.. I'm compiling with MinGW on Windows and I have SFML and OpenGL as dependencies.
And no, the -s flag is nowhere to be found in my makefile.
Ahh. I'm very sorry. It turns out the "clean:" portion of my makefile is broken. Thus when I used make clean nothing happened. Deleting the .o files manually fixed the problem. The flags work perfectly now. Thanks to everyone who posted anyway! This can be deleted now.
I had the same issue when using a makefile I inherited on some old F77 code. I tried all the flags people recommend (-g -ggdb ...etc.)
the solution was run make clean
If you don't have that or know what it means, basically delete all the compiled (.o) files.
the makefile didn't know to recompile since only flags were changed, so I wasn't actually compiling with -g or -ggdb when I thought it was. Hope this helps someone!
try to replace
$(BIN): $(OBJ)
$(CPP) $(LDFLAGS) $(OBJ) -o $(BIN) $(LIBS)
with
$(BIN): $(OBJ)
$(CPP) $(CFLAGS) -o $(BIN) $(OBJ) $(LDFLAGS) $(LIBS)
(edit)
Note: -c option will not work with executable
I dont have much experience with Mingw but try replacing -g with -ggdb. This may solve your problem. According to gcc man page
Produce debugging information for use
by GDB. This means to use the most
expressive format available (DWARF 2,
stabs, or the native format if neither
of those are supported), including GDB
extensions if at all possible.
I think you need -g when linking the object into a binary code.
CPP = g++
CFLAGS = -g -Wall
$(BIN): $(OBJ)
$(CPP) $(CFLAGS) $(OBJ) -o $(BIN) $(LDFLAGS) $(LIBS)
<test.o>: <test.cpp>
$(CPP) $(CFLAGS) -c <test.cpp> -o <test.o>
I am not sure, but I think you need -g even while linking.
Related
I am working with an ecological model PEAT-DOS-TEM. I am working in Vagrant ubuntu/trusty64 on a PC. The code I got from GitHub has a Makefile. When i run the command "make" I get this error as a result:
"make: *** No rule to make target 'obj/TEM.o', needed by 'dos-tem'. Stop."
I didn't write this makefile and I don't know C++ very well, if you know how to help me please explain as you would to a beginner. Thank you.
Here is my Makefile:
CC=g++
CFLAGS= -c -Wall -ansi -O0 -g -fPIC
LIBS=-lnetcdf_c++ -lnetcdf
LIBDIR=-Lnetcdf/libs
INCLUDES=-Inetcdf/includes
SOURCES= src/TEM.o \
src/atmosphere/AtmosUtil.o \
OBJECTS= TEM.o\
AtmosUtil.o \
GIT_SHA := $(shell git describe --abbrev=6 --dirty --always --tags)
TEMOBJ= obj/TEM.o
dos-tem: $(SOURCES) $(TEMOBJ)
$(CC) -o peat-dos-tem $(OBJECTS) $(TEMOBJ) $(LIBDIR) $(LIBS)
lib: $(SOURCES)
$(CC) -o libDOSTEM.so -shared $(INCLUDES) $(OBJECTS) $(LIBDIR) $(LIBS)
.cpp.o:
$(CC) $(CFLAGS) $(INCLUDES) $<
clean:
rm -f $(OBJECTS) DVMDOSTEM TEM.o libDOSTEM.so* *~
You have asked make to build a file obj/TEM.o:
TEMOBJ= obj/TEM.o
dos-tem: $(SOURCES) $(TEMOBJ)
(why do you list $(SOURCES) as a prerequisite?) but you have no rule to build that file. This rule:
.cpp.o:
$(CC) $(CFLAGS) $(INCLUDES) $<
will tell make how to build a file X.o from a file X.cpp; in your case the X is obj/TEM so this rule only works if make can find (or build) a file named obj/TEM.cpp which it can't.
So, turns out the Vagrant box I was using just needed to be updated. The original code is working. Thanks for all the help.
First check if you have installed c++ compiler by typing g++ in terminal.
Than to compile type in terminal: gcc sourcefile_name.cpp -o outputfile.exe
Finally, to run the code, type: outputfile.exe
Hope it helped
My make file is failing to find my include directory when it tries to remake object files. For example, when I call make tests I get the output:
g++ -c -o sdl_class.o sdl_class.cpp
sdl_class.cpp:9:23: fatal error: sdl_class.h: No such file or directory
#include <sdl_class.h>
^
compilation terminated.
make: *** [sdl_class.o] Error 1
My Makefile is this:
#Originally from: http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/
#But will be heavily modified
IDIR =../include
CC=g++
CFLAGS=-w -I$(IDIR)
#ODIR=obj
LDIR =../lib
LIBS=-lSDL2
_DEPS = sdl_class.h SDL_image.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
OBJ = sdl_class.o tests.o
#OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
%.o: %.cpp $(DEPS)
$(CC) -c -o $# $< $(CFLAGS) $(LIBS)
tests: sdl_class.o tests.o
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
all: $(OBJ)
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f *.o *~ core $(IDIR)/*~
My understanding is that when I call make tests, that it should attempt to remake the sdl_class.o file. This should then call the %.o rule, which should try to make the object file by calling something like:
g++ -c -o sdl_class.o sdl_class.cpp -w -I../include -lSDL2
However, this is not the case as it looks like it is calling $(CC) -c -o $# $< $(CFLAGS) $(LIBS), as you can see from above.
Do I have a fundamental misunderstanding about how make builds its rules? Seems likely, this is my first Makefile. Perhaps I am confused on how compilation works in general, as I'm somewhat new to that as well.
I would say that the problem is that one or more of the files ../include/sdl_class.h or ../include/SDL_image.h does not exist. Because of that, make is deciding that your pattern rule does not match (because not all the prerequisites can be found or made) and it defaults to the built-in rule to create object files from .cpp files.
The built-in rules use the make variables CXX for the C++ compiler and CXXFLAGS for the C++ flags: the CC and CFLAGS variables are used for the C compiler. That's why your settings for CFLAGS are being ignored.
If you run make -d sdl_class.o you'll see which file make is looking for and why it decides to not use your pattern rule.
If you rewrite your rules like this it will work better:
%.o: %.cpp
$(CC) -c -o $# $< $(CFLAGS)
sdl_class.o tests.o: $(DEPS)
because make will now complain that the relevant files can't be found or created.
There are other issues, of course. You shouldn't be passing $(LIBS) to your compile command; that belongs only in your link line. And, you should probably stick to the standard variables CXX for the C++ compiler, CPPFLAGS for preprocessor flags like -I and -D, and CXXFLAGS for C++ compiler flags. Also, linker library flags like -L../lib go in LDFLAGS and linker libraries like -lSDL2 go in LDLIBS.
CC/CCFLAGS are for C compilation. You should use CXX and CXXFLAGS for C++. They are used in built-in rules and in the LINK.cc macro, making the Makefile much simpler, and thus less error prone.
CXXFLAGS = -Wall ...
prog : foo.o bar.o
$(LINK.cc) -o $# $^
see Default linker setting in Makefile for linking C++ object files
My Makefile looks as follows:
CXX = g++
CXXFLAGS = -g
INCLUDES = -Iinclude/
OBJS = a1.o \
b1.o
LIBPATH= /usr/lib/<arch>
test-app:$(OBJS)
$(CXX) -o $# $(OBJS)
%.o : %.cpp
$(CXX) $(INCLUDES) -c $(CXXFLAGS) $< -o $#
I want to link two files lib1.so and lib2.so present in LIBPATH? Can anyone please help me with the syntax?
The syntax is
test-app:$(OBJS)
$(CXX) -o $# $(OBJS) -Lpath_to_your_lib -lyour_libname
Also you should use pkg-config to find those variables value.
Try this one:
LIBRARIES= -llib1 -llib2
...
test-app:$(OBJS)
$(CXX) -o $# -L$(LIBPATH) $(LIBRARIES) $(OBJS)
Consider that the arguments order are most of times important since the gcc compiler/linker process the files just one time in the given order and if the order was wrong errors like "Symbol not find" and "undefined reference" will be produced.
Though, I strongly recommend CMake since it's syntax is so easier, more dynamic and It supports many build platforms (IDEs, Compilers, Makefiles, etc.)
Update:
This configuration is likely more effective than the above:
SHARED_LIBRARIES= -L/path/to/shared_libs -llib1 -llib2
STATIC_LIBRARIES= -L/path/to/static_libs -llib1 -llib2 -L/another/path/to/static_libs -llib3
...
test-app:$(OBJS)
$(CXX) -o $# $(STATIC_LIBRARIES) $(SHARED_LIBRARIES) $(OBJS)
can compiler options be applied selectively on my files?
I want some files to be covered by some option but not the other files.
Guessing that you might be using Make files:
This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1.exe
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2
Of course. You invoke the compiler, and you can tell it what you want.
Some tools may add some restrictions; Visual Studio, as far as I know, only allows specifying options at the project level. But that's an artificial restriction of the tool (and I'm sure there are ways around it—I just don't know them).
I have a makefile that can be reduced to this:
OBJS = obj1.o obj2.o
FLAGS = -Wall -Wextra -Werror -pedantic-errors -fno-rtti -std=c++0x
DEBUG_FLAGS = -ggdb -O0 -fstack-protector-all -D_GLIBCXX_DEBUG
RELEASE_FLAGS = -O3
release: $(OBJS)
g++ $(FLAGS) $(RELEASE_FLAGS) $(OBJS)
debug: $(OBJS)
g++ $(FLAGS) $(DEBUG_FLAGS) $(OBJS)
obj1.o: obj1.cpp
g++ -c $(FLAGS) obj1.cpp
obj2.o: obj2.cpp
g++ -c $(FLAGS) obj2.cpp
The problem is that all or none of the files must be built with the -D_GLIBCXX_DEBUG flag. I don't know how to do this without writing two entries for every compilation unit, like
obj1_release.o: obj1.cpp
g++ -c $(FLAGS) $(RELEASE_FLAGS) obj1.cpp
obj1_debug.o: obj1.cpp
g++ -c $(FLAGS) $(DEBUG_FLAGS) obj1.cpp
How can I make the -D_GLIBCXX_DEBUG flag (and the other debug flags) take effect for all compilation units only when the user types make debug without writing two entries for every CU? (And vice versa; the release flags need to take effect on all CUs when the user types make release.)
I apologise if this is the basics of writing Makefiles, I don't know much about them.
You are looking for pattern rules: something like this should do what you want. Note that this cannot be made to work correctly unless the debug and release versions of the program are given different names.
OBJS := obj1 obj2 obj3
R_OBJS := $(OBJS:=_r.o)
D_OBJS := $(OBJS:=_d.o)
all: prog_r prog_d
release: prog_r
debug: prog_d
prog_r: $(R_OBJS)
$(CXX) $(CXXFLAGS) $(RELEASE_FLAGS) $(LDFLAGS) $^ $(LIBS) -o $#
prog_d: $(D_OBJS)
$(CXX) $(CXXFLAGS) $(DEBUG_FLAGS) $(LDFLAGS) $^ $(LIBS) -o $#
%_r.o: %.cc
$(CXX) $(CXXFLAGS) $(RELEASE_FLAGS) -c $< -o $#
%_d.o: %.cc
$(CXX) $(CXXFLAGS) $(DEBUG_FLAGS) -c $< -o $#
# header files
obj1_d.o obj1_r.o: foo.h bar.h
obj2_d.o obj2_r.o: quux.h
# ... etc ...
There is a pretty straightforward way to select compilation flags based on the type of the build in Makefiles.
In addition to that you may like to ensure that debug build only links debug object files and same for release (i.e. no mixing debug and release object files). To achieve that compile object into different directories depending on the build type.
This might help : http://sunsite.ualberta.ca/Documentation/Gnu/make-3.79/html_chapter/make_7.html
You could check the first argument (debug/release) and set the CFLAGS accordingly.
HTH.