Why am I getting the error message undefinded reference to 'omp_get_wtime' when I try to build my cpp file?
The full error message looks like this:
C:\Program Files\JetBrains\CLion 2022.2.4\bin\mingw\bin/ld.exe:
C:\Users\Hannah\AppData\Local\Temp\ccp3nN8r.o:daxpy.cpp:(.text+0x629): undefined reference to 'omp_get_wtime'
collect2.exe: error: ld returned 1 exit status
I looked into various posts already and most of them say to link -fopenmp in the makefile, but I already did that (it was done for us students).
My Makefile looks like this:
CC=gcc
CXX=g++
CFLAGS=-O3 -fopenmp -std=c99
CXXFLAGS=-O3 -fopenmp
EXECS=daxpy
all: $(EXECS)
matmul_serial-sol: daxpy.cpp
$(CXX) -o $# $< $(CXXFLAGS)
clean:
rm -f $(EXECS) *.o
and after suggestions from the comments:
CC=gcc
CXX=g++
CFLAGS=-O3 -fopenmp -std=c99
CXXFLAGS=-O3 -fopenmp
LDFLAGS= -fopenmp
EXECS=daxpy
all: $(EXECS)
daxpy: daxpy.cpp
$(CXX) -o $# $< $(CXXFLAGS)
clean:
rm -f $(EXECS) *.o
and I did include omp.h in my file.
Related
NOTE PLEASE: I read the question and their answers but still, I haven't found any answer to my problem so I had to ask this question.
I have a macOS and kali Linux laptop and when I compaile this same code in my iMac the code work fine (I have some errors in exeption but I'm trying to fix them).
but when I tried to compaile the same code in my kali linux I got the following error:
└─$ make 1 ⨯
g++ -Wall -Wextra -Werror -I. -c -o main.o main.cpp
g++ -Wall -Wextra -Werror -I. -c -o Bureaucrat.o Bureaucrat.cpp
clang++ -Wall -Wextra -Werror -I. -o Bureaucrat main.o Bureaucrat.o -I Bureaucrat.hpp
/usr/bin/ld: cannot find -lstdc++
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [Makefile:27: Bureaucrat] Error 1
my makefile:
SRCS = main.cpp \
Bureaucrat.cpp \
OBJS = $(SRCS:.cpp=.o)
CPP = clang++
RM = rm -f
CPPFLAGS = -Wall -Wextra -Werror -I.
NAME = Bureaucrat
all: $(NAME)
$(NAME): $(OBJS) Bureaucrat.hpp
$(CPP) $(CPPFLAGS) -o $(NAME) $(OBJS) -I Bureaucrat.hpp
clean:
$(RM) $(OBJS)
fclean: clean
$(RM) $(NAME)
re: fclean $(NAME)
.PHONY: all clean fclean re
I've started to code on Visual Studio Code (I was coding on IDE before) and to make project I learned that you need to do a makefile to link the file in your project.
So i searched a lot of tuto and i come up with this:
DEBUG=yes
CXX=g++
ifeq ($(DEBUG),yes)
CXXFLAGS=-W -Wall -ansi -pedantic -g
LDFLAGS=
else
CXXFLAGS=-W -Wall -ansi -pedantic
LDFLAGS=
endif
OBJDIR:= obj
EXECDIR:= bin
VPATH=src
EXEC=$(VPATH)/prog
SRC= $(wildcard src/*.cpp)
OBJECTS= main.o hello.o
OBJ= $(addprefix $(OBJDIR)/,$(OBJECTS))
all : $(EXEC)
ifeq ($(DEBUG),yes)
#echo "Generation en mode debug"
else
#echo "Generation en mode release"
endif
$(EXECDIR)/$(EXEC): $(OBJ) | $(EXECDIR)
$(CXX) $(CXXFLAGS) -o $# $^
$(EXECDIR):
mkdir $(EXECDIR)
$(OBJDIR)/main.o: src/hello.hpp
$(OBJDIR)/hello.o: src/hello.hpp
$(OBJDIR)/%.o: src/%.cpp | $(OBJDIR)
#$(CXX) -o $# -c $< $(CXXFLAGS)
$(OBJDIR):
mkdir $(OBJDIR)
.PHONY: clean mrproper
clean:
#rm -rf *.o
mrproper: clean
#rm -rf $(EXEC)
but I have a little problem ...
xe: cannot open output file /prog.exe: Permission denied
collect2.exe: error: ld returned 1 exit status
mingw32-make: *** [makefile:26: /prog] Error 1
And i really don't know why it is doing this
I am trying to build a Makefile that will build a shared library with g++ and I find that it is not evaluating the OBJECTS variable. This is on Ubuntu 18.04 and all the files are in the same current directory. Secondly it is completely skipping the source file compilation and proceeding directly to evaluate the linking instruction. As a clarification I am using GNU Make 4.1
Here is what I get when I type make all
g++ -shared -pthread -o tree.so
g++: fatal error: no input files
compilation terminated.
Makefile:12: recipe for target 'tree.so' failed
make: *** [tree.so] Error 1
Here is my Makefile code
CC=g++
CFLAGS = -I/usr/local/include -Wall -std=c++17 -O3 -march=native -Ofast -ftree-vectorize
LIBS=-shared -pthread
SOURCES=$(wildcard *.cpp)
OBJECTS=$(wildcard *.o)
TARGET=tree.so
all:$(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(OBJECTS) $(TARGET)
$(OBJECTS):$(SOURCES)
$(CC) -c -g $(CFLAGS) $(SOURCES)
clean:
rm -f $(OBJECTS) $(TARGET)
If you only have the *.cpp files in your directories, then there is not any *.o yet, so your $(wildcard *.o) will expand to nothing.
What you want is to get the *.cpp files and compute the corresponding *.o files:
OBJECTS=$(patsubst %.cpp,%.o,$(SOURCES))
or equivalently:
OBJECTS=$(SOURCES:.cpp=.o)
Now, your compiler command is not the best one, because if you touch any source file all will be compiled. You can use instead:
$(OBJECTS): %.o: %.cpp
$(CC) -c -g $(CFLAGS) $< -o $#
So that only the touched files are actually rebuilt.
Also you have the linking command wrong. It should be:
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(TARGET) $(OBJECTS)
because the argument to the -o option is the output file, that is the target.
After try to use this attached makefile the error that appears is :
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
make: *** [Ass1F] Error 1
the makefile is :
all: Ass1F
Ass1F: bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
g++ -o bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
#echo 'Finished building target: Ass1F'
#echo ' '
bin/x.o: src/x.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/x.o src/x.cpp
bin/y.o: src/y.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/y.o src/y.cpp
bin/z.o: src/z.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/z.o src/z.cpp
bin/w.o: src/w.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/w.o src/w.cpp
bin/main.o: src/main.cpp
g++ -g -Wall -Weffc++ -c -Linclude -o bin/main.o src/main.cpp
clean:
rm -f bin/*
what should I do with this problem?
the reason is the makefile or something in the code?
just to let you know we used eclipse to write the code and everything work perfectly- no any bugs.
thanks
Line g++ -o bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o tries to create executable named bin/main.o, overwriting its previous contents.
It should be e.g. g++ -o Ass1F bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
Your makefile recipe for Ass1F is incorrect, it doesn't specify the output file, os make uses bin/main.o as the output file instead of one of the input files.
You can simplify the makefile by using pattern rules (i.e. with wildcards) and using pre-defined variables such as $# (the name of the target) and $^ (the list of prerequisites) and CXX (the C++ compiler):
CXXFLAGS = -g -Wall -Weffc++
CPPFLAGS =
LDFLAGS =
LDLIBS =
all: Ass1F
Ass1F: bin/main.o bin/x.o bin/y.o bin/z.o bin/w.o
$(CXX) $(LDFLAGS) -o $# $^ $(LDLIBS)
#echo 'Finished building target: Ass1F'
#echo ' '
bin/%.o: src/%.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $^
clean:
rm -f bin/*
i have a simple Makefile:
CC=g++
CFLAGS= -Wall -std=c++11 -M -MF dependencyFileName.d -c
objects = Table.o LimitedTable.o aDimension.o test.o
edit: $(objects)
g++ -o edit $(objects)
test.o: LimitedTable.o Table.o aDimension.o test.cpp
$(CC) $(CFLAGS) test.cpp -o test.o
LimitedTable.o: LimitedTable.cpp LimitedTable.hpp Table.o aDimension.o
$(CC) $(CFLAGS) LimitedTable.cpp -o LimitedTable.o
aDimension.o: aDimension.cpp aDimension.cpp Table.o
$(CC) $(CFLAGS) aDimension.cpp -o aDimension.o
Table.o: Table.cpp Table.hpp
$(CC) $(CFLAGS) Table.cpp -o Table.o
clean:
rm -f *.o
and I get this error:
marius#marius-Lenovo-Y50-70 ~/Documents $ make clean
rm -f *.o
marius#marius-Lenovo-Y50-70 ~/Documents $ make edit
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c Table.cpp -o Table.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c aDimension.cpp -o aDimension.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c LimitedTable.cpp -o LimitedTable.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c test.cpp -o test.o
g++ -o edit Table.o LimitedTable.o aDimension.o test.o
Table.o: file not recognized: File truncated
collect2: error: ld returned 1 exit status
make: *** [edit] Error 1
Can anyone tell me what is wrong ?
Could a wrong include in one of the files be a reason for this error ?
There are some problems with the way you handle your dependency file, but first:
I have a simple Makefile
No you don't. The amount of boilerplate code is way too high, and adding any file to your projet will require you to manually edit that makefile again.
Your Makefile should be boiled down to this:
SRC := $(wildcard *.cpp)
OBJ := $(SRC:.cpp=.o)
DEP := $(OBJ:.o=.d)
CPPFLAGS := -MMD -MP
CXXFLAGS := -std=c++11 -Wall
edit: $(OBJ)
$(CXX) $^ -o $#
-include $(DEP)
clean:
$(RM) $(OBJ) $(DEP)
Here you :
avoid repeating yourself too much,
make good use of make's implicit rules to save time,
use the right built-in variables instead of overriding the wrong ones,
correctly handle dependency files creation and actually use them to prevent manual recompilation,
won't need to edit the makefile when adding a .cpp or .hpp file to your project.
Also, that should fix your problem. Don't forget to clean before trying to compile again after such an error ("file truncated") occurred.