I'm making a simple C++ project that uses two different programs (One sends information and the other receives it, if you're curious). I made a makefile to compile both programs and generate two executable files in one go, but when I execute my make instruction I get the following error:
makefile:51: atención: se anulan las instrucciones para el objetivo 'build/NetcpSend.o'
makefile:32: atención: se ignoran las instrucciones viejas para el objetivo 'build/NetcpSend.o'
g++ -c -o build/NetcpSend.o src/NetcpSend.cc -g -std=c++11
g++ -c -o build/generic_l.o src/generic_l.cc -g -std=c++11
g++ -c -o build/socket_c.o src/socket_c.cc -g -std=c++11
g++ -c -o build/file_c.o src/file_c.cc -g -std=c++11
g++ -o bin/NetcpSend build/NetcpSend.o build/generic_l.o build/socket_c.o build/file_c.o -g -std=c++11
make: *** No hay ninguna regla para construir el objetivo 'build/NetcpReceive.o', necesario para 'NetcpReceive'. Alto.
Translation:
makefile:51: warning: instructions cancelled for 'build/NetcpSend.o' objective.
makefile:51: warning: instructions cancelled for 'build/NetcpReceive.o' objective.
g++ -c -o build/NetcpSend.o src/NetcpSend.cc -g -std=c++11
g++ -c -o build/generic_l.o src/generic_l.cc -g -std=c++11
g++ -c -o build/socket_c.o src/socket_c.cc -g -std=c++11
g++ -c -o build/file_c.o src/file_c.cc -g -std=c++11
g++ -o bin/NetcpSend build/NetcpSend.o build/generic_l.o build/socket_c.o build/file_c.o -g -std=c++11
make: *** No rule to build 'build/NetcpReceive.o', needed for NetcpReceive. Stop.
And when I try to execute NetcpReceive, it obviously doesn't find the executable, because it hasn't compiled yet.
This is my makefile:
CC=g++
CFLAGS=-g -std=c++11
INCLUDE_DIR=include
OBJECTS_DIR=build
SRC_DIR=src
BIN_DIR=bin
_OBJ1 = NetcpSend.o generic_l.o socket_c.o file_c.o
OBJ1 = $(patsubst %,$(OBJECTS_DIR)/%,$(_OBJ1))
_OBJ2 = NetcpReceive.o generic_l.o socket_c.o file_c.o
OBJ2 = $(patsubst %,$(OBJECTS_DIR)/%,$(_OBJ2))
BIN_NAME1 = NetcpSend
BIN_NAME2 = NetcpReceive
all: All NetcpSend NetcpReceive
All:
$(OBJECTS_DIR)/NetcpSend.o: $(SRC_DIR)/NetcpSend.cc
$(CC) -c -o $# $< $(CFLAGS)
$(OBJECTS_DIR)/generic_l.o: $(SRC_DIR)/generic_l.cc
$(CC) -c -o $# $< $(CFLAGS)
$(OBJECTS_DIR)/socket_c.o: $(SRC_DIR)/socket_c.cc
$(CC) -c -o $# $< $(CFLAGS)
$(OBJECTS_DIR)/file_c.o: $(SRC_DIR)/file_c.cc
$(CC) -c -o $# $< $(CFLAGS)
NetcpSend: $(OBJ1)
$(CC) -o $(BIN_DIR)/$(BIN_NAME1) $^ $(CFLAGS)
NetcpReceive: $(OBJ2)
$(CC) -o $(BIN_DIR)/$(BIN_NAME2) $^ $(CFLAGS)
$(OBJECTS_DIR)/NetcpSend.o: $(SRC_DIR)/NetcpSend.cc
$(CC) -c -o $# $< $(CFLAGS)
run: #Runs the code
./$(BIN_DIR)/$(BIN_NAME1)
./$(BIN_DIR)/$(BIN_NAME2)
dbg: #Debugs the code
gdb ./$(BIN_DIR)/$(BIN_NAME)
.PHONY: clean
clean:
#rm -f $(OBJECTS_DIR)/*.o $(BIN_DIR)/* $(BIN_DIR)/*
I don't know what's causing ths issue, and if my makefile is correct according to standards. Could someone give me a hand?
There is no rule for NetcpReceive.o, only NetcpSend.o and others.
Since all your object build recipes look alike you could/should declare a pattern rule:
$(OBJECTS_DIR)/%.o: $(SRC_DIR)/%.cc
$(CC) -c -o $# $< $(CFLAGS)
Your recipe for the executables can be improved too. Declare the recipe and set prerequisites separately:
# Prerequisites
$(BIN_DIR)/NetcpSend: $(OBJ1)
$(BIN_DIR)/NetcpReceive: $(OBJ2)
# Recipes
$(BIN_DIR)/NetcpReceive $(BIN_DIR)/NetcpSend:
$(CC) -o $# $^ $(CFLAGS)
I personally try not to mess with object and bin folders when using make.
Related
When I try this;
VPATH= ./src
CXXFLAGS= -I "./include"
program: ListNode.o LinkedList.o TreeNode.o Tree.o Test.o
g++ lib\ListNode.o lib\LinkedList.o lib\TreeNode.o lib\Tree.o lib\Test.o -o bin\program
ListNode.o: ListNode.cpp
g++ -c $(CXXFLAGS) $< -o lib\ListNode.o
LinkedList.o: LinkedList.cpp
g++ -c $(CXXFLAGS) $< -o lib\LinkedList.o
TreeNode.o: TreeNode.cpp
g++ -c $(CXXFLAGS) $< -o lib\TreeNode.o
Tree.o: Tree.cpp
g++ -c $(CXXFLAGS) $< -o lib\Tree.o
Test.o: Test.cpp
g++ -c $(CXXFLAGS) $< -o lib\Test.o
clean:
del *.exe
del *.o
It all works without any problem.But for my homework I have to create a static library.Anyway when I add this command to the makefile;
VPATH= ./src
CXXFLAGS= -I "./include"
program: ListNode.o LinkedList.o TreeNode.o Tree.o Test.o
g++ lib\ListNode.o lib\LinkedList.o lib\TreeNode.o lib\Tree.o lib\Test.o -o bin\program
ListNode.o: ListNode.cpp
g++ -c $(CXXFLAGS) $< -o lib\ListNode.o
LinkedList.o: LinkedList.cpp
g++ -c $(CXXFLAGS) $< -o lib\LinkedList.o
TreeNode.o: TreeNode.cpp
g++ -c $(CXXFLAGS) $< -o lib\TreeNode.o
Tree.o: Tree.cpp
g++ -c $(CXXFLAGS) $< -o lib\Tree.o
Test.o: Test.cpp
g++ -c $(CXXFLAGS) $< -o lib\Test.o
clean:
del *.exe
del *.o
libclass.a: ListNode.o LinkedList.o
ar -rcs libclass.a lib\ListNode.o lib\LinkedList.o
It doesn't do anything.There is no file or there is no error.Its like it doesn't exist :/
By the way I think it'd be good to mention about that if I use first makefile and then I put this code on terminal;
ar -rcs libclass.a lib\*.o
It works like magic i mean perfectly.So I need a little bit help cuz I'm about to go insane.Any help would be appreciated.
Add:
all: program libclass.a
to the beginning of your makefile. By default, make builds only the first target it finds in your makefile. This declares a fake target named "all" that depends on "program" and "libclass.a", so make ends up building both.
i have a simple Makefile:
CC=g++
CFLAGS= -Wall -std=c++11 -M -MF dependencyFileName.d -c
objects = Table.o LimitedTable.o aDimension.o test.o
edit: $(objects)
g++ -o edit $(objects)
test.o: LimitedTable.o Table.o aDimension.o test.cpp
$(CC) $(CFLAGS) test.cpp -o test.o
LimitedTable.o: LimitedTable.cpp LimitedTable.hpp Table.o aDimension.o
$(CC) $(CFLAGS) LimitedTable.cpp -o LimitedTable.o
aDimension.o: aDimension.cpp aDimension.cpp Table.o
$(CC) $(CFLAGS) aDimension.cpp -o aDimension.o
Table.o: Table.cpp Table.hpp
$(CC) $(CFLAGS) Table.cpp -o Table.o
clean:
rm -f *.o
and I get this error:
marius#marius-Lenovo-Y50-70 ~/Documents $ make clean
rm -f *.o
marius#marius-Lenovo-Y50-70 ~/Documents $ make edit
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c Table.cpp -o Table.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c aDimension.cpp -o aDimension.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c LimitedTable.cpp -o LimitedTable.o
g++ -Wall -std=c++11 -M -MF dependencyFileName.d -c test.cpp -o test.o
g++ -o edit Table.o LimitedTable.o aDimension.o test.o
Table.o: file not recognized: File truncated
collect2: error: ld returned 1 exit status
make: *** [edit] Error 1
Can anyone tell me what is wrong ?
Could a wrong include in one of the files be a reason for this error ?
There are some problems with the way you handle your dependency file, but first:
I have a simple Makefile
No you don't. The amount of boilerplate code is way too high, and adding any file to your projet will require you to manually edit that makefile again.
Your Makefile should be boiled down to this:
SRC := $(wildcard *.cpp)
OBJ := $(SRC:.cpp=.o)
DEP := $(OBJ:.o=.d)
CPPFLAGS := -MMD -MP
CXXFLAGS := -std=c++11 -Wall
edit: $(OBJ)
$(CXX) $^ -o $#
-include $(DEP)
clean:
$(RM) $(OBJ) $(DEP)
Here you :
avoid repeating yourself too much,
make good use of make's implicit rules to save time,
use the right built-in variables instead of overriding the wrong ones,
correctly handle dependency files creation and actually use them to prevent manual recompilation,
won't need to edit the makefile when adding a .cpp or .hpp file to your project.
Also, that should fix your problem. Don't forget to clean before trying to compile again after such an error ("file truncated") occurred.
I'm trying to compile my project using a Makefile, but somehow the -fopenmp flag won't work.
Here's the Makefile:
TARGET=isaac
CC=g++
CFLAGS=-Wall -O2 -fopenmp
LDFLAGS=-lm -lpthread -lrt
OBJ=src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o
isaac: $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
clean:
rm src/*.o src/*~ isaac
and here is the output when calling "make"
g++ -c -o src/main.o src/main.cpp
g++ -c -o src/bhtree.o src/bhtree.cpp
g++ -c -o src/body.o src/body.cpp
g++ -c -o src/configreader.o src/configreader.cpp
g++ -c -o src/diagnostics.o src/diagnostics.cpp
g++ -c -o src/output.o src/output.cpp
g++ -c -o src/quad.o src/quad.cpp
g++ -c -o src/timing.o src/timing.cpp
g++ -c -o src/vector2.o src/vector2.cpp
g++ -Wall -O2 -fopenmp -o isaac src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o -lm -lpthread -lrt
the -fopenmp flag is missing when the source files are compiled, so the finished executable is serial, not parallel.
How can I fix this?
The problem is that your rule does not apply at all. You are free to remove
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
and you'll get the same result as before. That's because some predefined rule is used instead of yours (I'm not great makefile expert though).
The core of the problem is that your rule is for ./*.o files, but you need ./src/*.o for isaac. You can change your rule
src/%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
Or (better) move all autogenerated staff somewhere from src.
Here is makefile:
CC=g++
CC_FLAGS=-Wall -march=native -ffast-math -O3
CC_SOURCES=AbsNode.cpp rle16.cpp
CC_OBJECTS=AbsNode.o rle16.o
# Link command:
test : $(CC_OBJECTS)
$(CC) $(CC_OBJECTS) -o test
# Compilation commands:
%.o:%.cpp
$(CC) -c $(CC_FLAGS) $(input) -o $(output)
when applying make to this makefile, I get the following output:
g++ -c -Wall -march=native -ffast-math -O3 -o
g++: arguemnt to '-o' missing
Why are inputs and outputs ignored???
You haven't defined the variables input and output anywhere. The computer is not a magic box that can guess your intentions.
Your .cpp -> .o implicit rule is incorrect:
%.o: %.cpp
$(CC) -c $(CC_FLAGS) $< -o $#
$< is set by make to be the source file
$# will be the output file name
I have the following makefile:
CC = gcc
SRC = source1.c
EXE = source1
FLAGS = -fopenmp
all: $(src)
$(CC) -o $(EXE) $(SRC) $(FLAGS)
clean:
rm $(EXE)
How can I modify it so I can use multiple sources, some of them compiled with the flag -fopenmp, some of them compiled without. Thanks a lot.
This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2
You can define for example, EXTFLAGS=$(FLAGS) -fopenmp, and use EXTFLAGS for some rules.