Just taking a use case for this instance. I'm compiling a c++ file, and sometimes, I'd like to compile without debugging symbols i.e. the -g enabled and sometimes I would like to enable it.
So, I thought of just making two targets in which the second target would reassign a make variable(is it possible) and change the compiling options. I wonder if such a behaviour is possible to achieve with makefiles?
Below is some pseudocode demo and the user enters make first#bg into the command line:
gpp = g++ -std=c++17
first: hello.cpp
$(gpp) hello.cpp -o $#
#/* some other recipes, assuming the list is really long*/
first#bg: main.o
gpp = g++ -g -std=c++17
execute_all_recipe_of_first_target_which_is_really_long_to_copy()
main.o: main.cpp
$(gpp) main.cpp -c -o main.o #the value of gpp should'd also changed here since first#bg executed
If it is possible please provide me with the actual syntax for the demonstrated behaviour. Thanks in advance.
You can do something like this:
first#bg: gpp += -g
first#bg: first
Note that it's more idiomatic to define CXX=g++ and CXXFLAGS=-std=c++17 and then tweak CXXFLAGS, and use make DEBUG=1 for debug builds:
CXX=g++
CXXFLAGS=-std=c++17
ifeq ($(DEBUG), 1)
CXXFLAGS+=-g
endif
Then invoke the compiler as $(CXX) $(CXXFLAGS) hello.cpp -o $# for example. See also this link
Related
I need help configuring my makefile to use it with the GNU debugger. I am running it on debian.
I am quite new to makefiles and after going through similar questions I've tried adapting the answers of those to my code, but it didn't work out the ways I tried (probably because i don't fully understand the syntax of makefiles).
This is the original (shortened) makefile:
INC=-I include
all: libs poisson_solver
poisson_solver:
g++ -o bin/poisson $(INC) src/main.c\ src/problem_setup.c\ libs/timer_tools.o
libs: libs/timer_tools.o src/problem_setup.o
libs/timer_tools.o: utilities/gettime.c
g++ -c -o libs/timer_tools.o $(INC) utilities/gettime.c
src/problem_setup.o: src/problem_setup.c include/problem_setup.h
g++ -c -o src/problem_setup.o $(INC) src/problem_setup.c include/problem_setup.h
Your Makefile has several errors, and in general contains more cruft than it should.
Here is roughly what it should be:
CFLAGS = -Iinclude -g
OBJS = src/main.o src/problem_setup.o utilities/gettime.o
all: poisson_solver
poisson_solver: $(OBJS)
src/problem_setup.o: src/problem_setup.c include/problem_setup.h
See this section of the manual.
Got an assignment to write a simple program in c++11 which contains the following files:
main.cpp
house.h
tree.h
The main function is obviously in the main.cpp file.
main.cpp includes the 2 header files and uses them.
when I tried to compile on Linux, I wrote:
g++ -std=c++11 -O2 -Wall -pedantic -pthread main.cpp -o prog
And I got a prog file which I could run.
Then I tried to compile it using a makefile, what I did was this:
all:
g++ -std=c++11 -O2 -Wall -pedantic -pthread main.cpp -o prog
and hit make all
Sadly it doesn't work.
Tried to search the web for how to do it properly, no luck.
Can you tell me how it needs to be done?
Also, how to make a smart compile? i.e. compile only when the above files are changed.
Thanks!
Create a Makefile with just the following lines and check this out:
CFLAGS += -g -O2 -Wall -W -pedantic
CXXFLAGS=$(CFLAGS) -std=c++11
CFLAGS += -pthread
LDFLAGS += -pthread
And type make main. Make will search its built-in rules and discover that there is a way to get from main.cpp to a compiled program named main. It will then execute a built-in rule that looks something like:
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $#
If you want to just type make then you can add:
all: main
And the built-in implicit rules will build main for you when you type make.
In Makefile
all:
<TAB>g++ -std=c++11 -O2 -Wall -pedantic -pthread main.cpp -o prog
This will work, Please pay attention here that <TAB> is the tab character that we need to insert.
Simply compiled it by issuing
make
Or for a simple cases, make provides a short cut with default rule. You can compile our code without using Makefile.
CXXFLAGS=-std=c+=11 -Wall -pedantic -pthread make main
But this approach will name the program name as name of the file, i.e. main here, instead of prog as you wanted
I have made a Makefile for my CMSC 202 course project, 'Blackjack'. It does everything I need it to and it works perfectly. You may be asking why I posted here then, this is because I have no idea how it works and I didn't use any other resources but myself to create it.
Here is my Makefile code.
# Object files to either reference or create
OBJECTS = Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
# The executable file that will be created at the end
EXEC = Proj2.out
# The flags to use for compilation
FLAGS = -Wall
# The code compiler to use for compilation
CC = g++
# Perform action on all object files (May or may not exist)
all: $(OBJECTS)
$(CC) $(FLAGS) -o $(EXEC) $(OBJECTS)
Here is the terminal output when I call make in the terminal.
g++ -c -o Proj2.o Proj2.cpp
g++ -c -o Blackjack.o Blackjack.cpp
g++ -c -o Deck.o Deck.cpp
g++ -c -o Card.o Card.cpp
g++ -c -o Hand.o Hand.cpp
g++ -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Can anyone tell me how the .o files are being compiled? It does not look like they are being prompted to be compiled with that g++ -c -o $.o $.cpp command anywhere in the Makefile. Nor did I state to use any .cpp files.
Thank you in advance for your help.
Edit
Thanks to all your great help, this is now the terminal output I receive when using make.
g++ -Wall -c -o Proj2.o Proj2.cpp
g++ -Wall -c -o Blackjack.o Blackjack.cpp
g++ -Wall -c -o Deck.o Deck.cpp
g++ -Wall -c -o Card.o Card.cpp
g++ -Wall -c -o Hand.o Hand.cpp
g++ -Wall -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Thank you so much to all of you who have contributed.
Make has a set of implicit rules (see here for a reference). For instance
Compiling C++ programs
`n.o' is made automatically from `n.cc' or `n.C' with a command of the form
`$(CXX) -c $(CPPFLAGS) $(CXXFLAGS)'.
Most make's will also use this rule for .cpp files.
When make sees there's a x.o requirement for one of your targets, it will try to see if it can generate x.o using implicit rules, and in your case find it can do it starting from a .cpp file.
This Makefile uses implicit rules which are a great way to reduce duplication.
By default the first target will be built, here all. It depends on a number
of object files listed in a variable $OBJECTS, e.g. Proj2.o who's
dependencies aren't listed in the Makefile. Now if make sees an input file in the current directory
with a matching name, e.g. Proj2.cpp it will try
to build Proj2.o from it (there are other implicit rules for sources in
other languages). Proj2.o would then be built by default with the command
$(CXX) $(CXXFLAGS) -c -o Proj2.o
where $(CXX) the name of the C++ compiler (g++ in your case).
The explicit build step for all assembles all the object files into the
target executable.
Looking at above build command you'll notice a small problem in your Makefile. Since the flags to the C++ compiler are given in a variable FLAGS and not the standard CXXFLAGS no warnings will be emitted when building the object files. Using the standard name would fix this (you do want warnings, maybe even more than -Wall gives you).
When I want to compile, I need to specify -std=c++11 like this:
g++ -Wall -std=c++11 main.cpp -o main
and I wonder if there was a solution to set the -std=c++11 flag permanently so it will be possible to do:
g++ -Wall main.cpp -o main
without flags.
Create an alias: alias g++='g++ -std=c++11' should do the trick.
(However, the version of GCC that comes with OS X is so ancient that it doesn't support C++11, you'd be better off using clang and clang++.)
I know this already has an accepted but I feel like I have some advice to offer. For one you should be using a makefile for c++, this is the one I use for answering on SO.
CFLAGS=-std=c++11
CFLAGS+=-stdlib=libc++
CC=clang++
#flags for test.c
cc=clang
DEBUG=-g
#warnings
WARNINGS=-Weverything
#always have -Weverything on for SO lol
OPT= -O0 -O1 -O2 -O3 -O4
test: test.cpp
$(info set CC for compiler)
$(CC) $(CFLAGS) $< -o $# $(DEBUG)
stack: stack.cpp
$(CC) $(CFLAGS) stack.cpp -o $# $(DEBUG) $(WARNINGS)
testc: test.c
$(cc) $< -o $# $(DEBUG)
clean:
rm test
Now whenever I download someones crappy code from SO I have a makefile for c and c++ files where I can easily change the flags if I want to.
As for bash alias I would suggest you alias it like so alias clang++11='clang++ -std=c++11 this way you don't overwrite the clang++ if you don't want to use the c++11 standard. Lastly you can add the line I just showed you to your .bash_profile on a mac which is in your home or ~ folder, this will make the change permanent. Once you change it run source .bash_profile to put the changes into effect. On linux I think the file is called .bashrc. Hopefully these tips will help you out when ur c++ing, I would advise you to learn the mac command line, has differences from the linux one, it can be very useful to know some of the things it can do.
I am taking a C++ course in college and they want us to manually type in all of the test files... I know, however, that there is a way to do it with out, which is how I ended up with the current(http://pastebin.com/6d9UtKM4) makefile. My question is, why is this makefile automatically removing all the .o files it uses for compiling when it is done? It's not killing me, but I would like to preserve the .o files. I have pasted the makefile here(http://pastebin.com/6d9UtKM4). I have also pasted the current result of running "make tests" here(http://pastebin.com/h3Ny3dib). (Note the part at the bottom of that page that removes all the .o files automatically.)
I would also like to be able to make it generate it like this:
g++ -o compileDir/assembler.o -c -Wall src/assembler.cpp
g++ -o compileDir/string.o -c -Wall src/string.cpp
g++ -c -Wall -o compileDir/test_assignment.o testSrc/test_assignment.cpp
g++ -o testDir/test_assignment compileDir/test_assignment.o compileDir/string.o compileDir/assembler.o
g++ -c -Wall -o compileDir/test_bracket.o testSrc/test_bracket.cpp
g++ -o testDir/test_bracket compileDir/test_bracket.o compileDir/string.o compileDir/assembler.o
testDir/test_bracket
testDir/test_assignment
In other words, I want it to compile everything, then run everything. I hope this isn't too much to ask!
Edit: Additional Information: (This is the code that does "make tests")
tests: assembler.o string.o $(test_output) $(test_stringOutput)
#echo '--- Testing complete ---'
$(testDir)%: $(compileDir)%.o string.o
g++ -o $# $< $(compileDir)string.o $(compileDir)assembler.o
$#
#echo ''
$(compileDir)%.o: $(testSourceDir)%.cpp
g++ -c -Wall -o $# $<
$(compileDir)%.o: $(testStringSrc)%.cpp
g++ -c -Wall -o $# $<
EDIT: -----------------------------------------
Resolved via comments:
Adding this line fixed it:
.PRECIOUS $(compileDir)%.o
You might add
.PRECIOUS: %.o
which should be implicit, but perhaps you've got a weird setup.
Make treats your .o files as intermediate and removes them. You can prevent automatic deletion of those by adding them a dependency of the special .SECONDARY target. See Chains of Implicit Rules for more details. Good luck!