How do I expend this Makefile to use wildcards? - c++

Question

I would like to adopt the following Makefile from this tutorial to more generic targets. For example, if I type make foo, then I expect an executable foo to be built from foo.v and foo.cpp in a process similar to that of making maskbus.
.PHONY: all
all: maskbus
obj_dir/Vmaskbus.cpp: maskbus.v
verilator -Wall -cc maskbus.v
obj_dir/Vmaskbus__ALL.a: obj_dir/Vmaskbus.cpp
make -C obj_dir -f Vmaskbus.mk
maskbus: maskbus.cpp obj_dir/Vmaskbus__ALL.a
g++ -I/usr/share/verilator/include -I obj_dir \
/usr/share/verilator/include/verilated.cpp \
maskbus.cpp obj_dir/Vmaskbus__ALL.a \
-o maskbus
.PHONY: clean
clean:
rm -rf obj_dir/ maskbus
Here is what I have tried
.PHONY: all
stuff: $(basename $(wildcard *.v))
all: stuff
obj_dir/%.cpp: %.v
verilator -Wall -cc $<
obj_dir/V%__ALL.a: obj_dir/V%.cpp
make -C obj_dir -f Vmaskbus.mk
stuff: $#.cpp obj_dir/V$#__ALL.a
g++ -I/usr/share/verilator/include -I obj_dir \
/usr/share/verilator/include/verilated.cpp \
$#.cpp obj_dir/V$#__ALL.a \
-o $#
.PHONY: clean
clean:
rm -rf obj_dir/ $(stuff)
Nota that I left the name Vmaskbus unchanged in the second rule as I have no idea how to extract the correct "basename" from a rule containing %. However, when I run make foo, that rule isn't even executed, and thus subsequent commands fail due to the absence of obj_dir/Vfoo__ALL.a. Some investigation suggests that the variable stuff is empty, but I'm sure I have both foo.v and foo.cpp in the current directory.

Answer 1

Figured it out myself:
.PHONY: all clean
stuff := $(basename $(wildcard *.v))
all: $(stuff)
obj_dir/V%.cpp: %.v
verilator -Wall -cc $<
obj_dir/V%__ALL.a: obj_dir/V%.cpp
make -C obj_dir -f V$*.mk
$(stuff): %: %.cpp obj_dir/V%__ALL.a
g++ -I /opt/local/share/verilator/include \
-I obj_dir \
-o $# \
/opt/local/share/verilator/include/verilated.cpp \
obj_dir/V$*__ALL.a \
$*.cpp
clean:
rm -rf obj_dir/ $(stuff)