verilog if-else error message - if-statement

Question

I have a problem with verilog if-else statement. I'm trying to make a digital clock and my tick_counter module code like this. I pointed to error line with comment line. I cant find the solve, please help me.
module tick_counter(
input clk,
input tick_in,
output [3:0] ssd_2, ssd_4,
output [2:0] ssd_3
);
reg [5:0] count1, count_next1;
reg [2:0] count2, count_next2;
reg [3:0] count3, count4, count_next3, count_next4;
always#(posedge clk)
begin
count1 <= count_next1;
count2 <= count_next2;
count3 <= count_next3;
count4 <= count_next4;
end
//next state logic
always#*
begin
if(tick_in)
begin
if(count1==6'b111100) //second counter
begin
count_next1 = 6'b0;
count_next2 = count2 + 1'b1;
end
else
count_next1 = count1 + 1'b1;
if(count2==4'b1001) //minutes counter of LSB digit
begin
count_next2 = 4'b0000;
count_next3 = count3 + 1'b1;
end
else
count_next2 = count2 + 1'b1;
if(count3==3'b101) //minutes counter of MSB digit
begin
count_next3 = 3'b000;
count_next4 = count4 + 1'b1;
end
else
count_next3 = count3 + 1'b1;
if(count4==4'b1001) //counter hour
begin
count_next4 = 4'b0000;
end
else
count_next4 = count4 + 1'b1;
else //---THE POINT OF ERROR------
begin
count_next1 = count1;
count_next2 = count2;
count_next3 = count3;
count_next4 = count4;
end
end
end
assign ssd_2 = count2;
assign ssd_3 = count3;
assign ssd_4 = count4;
endmodule

Answer 1

Of course endmodule is missing. But this may be your typo mistake.
Proper indentation is greatly encouraged for large designs. Here, after indenting your code, I came to know that one end after the else part of // counter hour condition is missing. So, your main if condition's end is mis-placed. Just add end at the specified position and remove one end from the last of always block.
Kindly do proper indentation so that it becomes easy to debug.