I'm trying to transform old project with Makefile to a modern one with CMakeLists.txt and GoogleTest framework but i can't handle the dependencies.
This is my Project structure
Project-LG
src/
app/
main.cpp
A.cpp
A.hpp
B.cpp
B.hpp
C.cpp
C.hpp
...
cpp-utils/
D.cpp
D.hpp
E.hpp
F.hpp
json/
json.hpp
hiredis/ /*Makefile project*/
orane2/ /*Makefile project*/
rmr/ /*Makefile project*/
spdlog/ /*Headers project with nested directories*/
Makefile
And this is the "Project-LG" Makefile
CC=gcc
CPP=g++
SRCDIR = .
APPDIR = $(SRCDIR)/app
UTILSDIR = $(SRCDIR)/cpp-utils
TARGETDIR =./../out
OBJDIR =./../out/obj
APP_OBJDIR =$(OBJDIR)/app
UTILS_OBJDIR =$(OBJDIR)/cpp-utils
LIBSDIR = ./../libs
INCLUDE_FILE = \
-Iapp \
-Icpp-utils \
-Irmr/si \
-Irmr/si/si95 \
-Irmr/common \
-Ijson \
-Iorane2 \
-I. \
-Ihiredis
SUBDIRS := \
$(SRCDIR)/rmr \
$(SRCDIR)/orane2 \
$(SRCDIR)/hiredis
LFLAGS =
LIBS += -pthread -static-libstdc++ \
-L$(LIBSDIR) -l:librmr.a -l:liborane2.a -l:hiredis.a
XAPP_NAME_STR := '"app-lg"'
CFLAGS += -Wall -g -O2 -DXAPP_NAME=$(XAPP_NAME_STR) $(INCLUDE_FILE)
CPPFLAGS = $(CFLAGS) -fPIC -std=c++17
APP_EXE ?= xapp
APP_SOURCES := $(shell find $(APPDIR) -maxdepth 1 -name '*.cpp' -printf '%f\n')
UTILS_SOURCES := $(shell find $(UTILSDIR) -maxdepth 1 -name '*.cpp' -printf '%f\n')
APP_OBJS := $(addprefix $(APP_OBJDIR)/, $(APP_SOURCES:%.cpp=%.o))
UTILS_OBJS := $(addprefix $(UTILS_OBJDIR)/, $(UTILS_SOURCES:%.cpp=%.o))
.SUFFIXES: .c~.o
.PHONY: all $(SUBDIRS) clean
all: $(SUBDIRS) $(APP_EXE)
$(APP_EXE): $(APP_OBJS) $(UTILS_OBJS)
#mkdir -p $(TARGETDIR)
#mkdir -p $(OBJDIR)
$(CPP) $(CFLAGS) $(LFLAGS) $(APP_OBJS) $(UTILS_OBJS) $(LIBS) -o $(TARGETDIR)/$#
$(APP_OBJDIR)/%.o : $(APPDIR)/%.cpp
#mkdir -p $(OBJDIR)
#mkdir -p $(APP_OBJDIR)
$(CPP) -c $(CPPFLAGS) $(LFLAGS) $< -o $#
$(UTILS_OBJDIR)/%.o : $(UTILSDIR)/%.cpp
#mkdir -p $(OBJDIR)
#mkdir -p $(UTILS_OBJDIR)
$(CPP) -c $(CPPFLAGS) $(LFLAGS) $< -o $#
$(SUBDIRS):
$(MAKE) -C $#
clean:
rm -rf $(TARGETDIR)
It was difficult to figure out how to call the Makefile from CMake and how to add the GoogleTest framework with all its dependencies
Please accept my thanks for your time.
I just started working with makefile.
I am getting the error with makefile of my C++ project.
make: No rule to make target 'bin/smartCart_app', needed by all.
Below is the directory structure and files associated with it.
VBOX:~BASE$ls
build src
VBOX:~BASE$cd build
VBOX:~BASE/build$ ls
bin build Makefile.sc
VBOX:~BASE/build$ cd ../src
VBOX:~BASE/src$ls
baseStation.cpp config util //config and util has header and cpp files
Here is my Make file
CC=gcc
CPP=g++
CCFLAGS=-g -Wall -std=gnu+0x -o0
CC_LDFLAGS = -g -Wl
BUILD=./build
BIN = ./bin
SC_SRC_ROOT = ../src
SC_SRC_SUBDIRS = config util
SC_SRC_RELDIRS = $(addprefix $(strip $(SC_SRC_ROOT)), $(strip $(SC_SRC_SUBDIRS)))
SC_SRCS_ = $(shell /usr/bin/find $(SC_SRC_ROOT)/config $(SC_SRC_ROOT)/util -name "*.cpp")
SC_SRCS = $(SC_SRCS_) baseStation.cpp
SC_NEW_SRCS = $(notdir $(SC_SRCS))
SPACE :=
SPACE +=
INCLUDE = $(addprefix -I, $(SRC_RELDIRS))
VPATH = $(subst $(SPACE),:,$(SRC_RELDIRS)) $(subst $(SPACE),:,$(SC_SRC_RELDIRS))
SC_INCLUDE = $(addprefix -I, $(SC_SRC_RELDIRS))
SC_OBJS = $(SC_NEW_SRCS:%.cpp=$(BUILD)/%.o)
SC_DEPS = $(SC_OBJS:%.o=%.d)
# Ensure paths exist.
$(shell [ -d "$(BIN)" ] || mkdir -p $(BIN))
$(shell [ -d "$(BUILD)" ] || mkdir -p $(BUILD))
# Explicit rules.
.PHONY: all clean $(PHONY)
all: $(BIN)/smartCart_app
clean:
#echo "Cleaning..."
-#rm -f $(BIN)/smartCart_app $(SC_OBJS)
$(SC_OBJS): $(BUILD)/%.o: %.cpp
#echo "Compiling $(notdir $<)"
#$(CPP) $(CCFLAGS) $(INCLUDE) $(SC_INCLUDE) -MD -c -o $# $<
$(MACRO_DEPS):
-#rm -f $(patsubst %_ON.d,%_OFF.d,$#) $(patsubst %_OFF.d,%_ON.d,$#) $#
#touch $#
#$(ALL_OBJS): %.o: %.d
$(DEPS): $(BUILD)/%.d: %.cpp
#$(CC) $< -MM -MF $# $(INCLUDE)
I'm using CODEO (Eclipse + overlay) to build an app for the ELinOS RTOS.
Thing is, I lose the ability to auto-generate the Makefile using eclipse CDT and I have a generic Makefile alreayd generated.
Instead of typing this huge Makefile (Lots and lots of include and sources directories), I tried things with addprefix patsubst and some wildcard but that didn't work out, mainly because I suck with generic makefile !
Regarding libraries, only a few are used, so I'll write them by hand.
Here is how my code is structured.
Top directory
|
---> common ---> inc/
| src/
---> pack_AAA ---> comp_AAA ---> inc/
| | src/
| ----> comp_AAB ---> inc/
| src/
---> comp_BBB ---> inc/
| src/
---> main.cpp
I'd like to enumerate only the top folders (common, pack_AAA, comp_BBB and so on, mostly because not every TOP folder has to be compiled, my Makefile is in one of these top folder).
Below there is a variable amount of subdirectories. Leafs are ALWAYS inc/ (.hpp files) and src/ (as you might guess, .cpp files) folders.
Moreover, the amount of TOP folders won't change, so I mind declaring them, but subfolders will.
Objects files can be anywhere they want (separate top build/ directory, within src/ ...) as long as the resulting executable, let's call it HUGE_PROJECT is in the top directory
Thanks in advance !
SOKS
Here is the generated makefile that I have to start with
-include makefile.init
RM := rm -rf
PROG = HUGE_PROJECT_EXECUTABLE
MODULES := common comp_AAA comp_BBB pack_AAA pack_BBB pack_CCC
SRC_DIRS := $(addprefix ../../,$(MODULES))
#BUILD_DIR := $(addprefix ../../build/,$(MODULES))
#Original non-recursive & working example
OBJS = $(patsubst %.cpp,%.o,$(wildcard ./src/*.cpp))
DEPS = $(patsubst %.cpp,%.d,$(wildcard ./src/*.cpp))
#bad attempt
#SRCS := $(foreach sdir,$(SRC_DIRS),$(wildcard $(sdir)/*.cpp))
#OBJS := $(patsubst %.cpp,%.o,$(SRCS))
#INCLUDES := $(addprefix -I,$(SRC_DIR))
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(DEPS)),)
-include $(DEPS)
endif
endif
-include makefile.defs
# All Target
all: $(PROG).tgz
$(PROG).tgz: $(PROG).mkefs $(PROG)
#echo 'Building file: $#'
#echo 'Invoking: Embeddable file system generator'
mkefs -a -s -o"$#" -f"$<"
#echo 'Finished building: $#'
#echo ' '
$(PROG): $(OBJS) $(USER_OBJS)
#echo 'Building target: $#'
#echo 'Invoking: ELinOS C/C++ Linker'
$(CXX) -o "$(PROG)" $(SRCS) $(USER_OBJS) $(LIBS)
#echo 'Finished building target: $#'
#echo ' '
clean:
-$(RM) $(OBJS) $(DEPS) $(PROG) $(PROG).tgz
-#echo ' '
./src/%.o: ./src/%.cpp
#echo 'Building file: $<'
#echo 'Invoking: ELinOS C/C++ Compiler'
$(CXX) -I./include -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
#echo 'Finished building: $<'
#echo ' '
.PHONY: all clean dependents
.SECONDARY:
-include makefile.targets
Here is the Makefile I ended up with.
I had to hide components name.
#Executables
RM := rm -rf
CXX=YOUR_CXX_COMPILER
CC=YOUR_CC_COMPILER
PROG=YOUR_PROGRAM
#Root directory of your program (all files should be in it)
ROOT_DIR := ../../
#####################################
########################################
# Define here all directories #
# containing src/ and inc/ folders #
########################################
#pack_AAA folders
#Modules containing both src/ and inc/.
AAA_MODULES := moduleA moduleB
#Modules with an include folder only + module with both
AAA_DIRS_INC := moduleD moduleEF $(AAA_MODULES)
#pack_BBB modules list
BBB_MODULES := comp_A comp_B comp_C comp_B/comp_D comp_B/comp_E
MMM_MODULES := comp_F comp_G comp_H
PPP_MODULES := . I
CCC_MODULES := J comp_K comp_L \
comp_L/comp_M \
$(addprefix pack_BBB/,$(BBB_MODULES)) \
$(addprefix pack_MMM/,$(MMM_MODULES)) \
$(addprefix comp_PPP/,$(PPP_MODULES))
#pack_DDD
DDD_MODULES := M comp_N comp_N/comp_O
#comp_EEE
EEE_MODULES := . P Q
OTHER_MODULES := R S comp_T
#All folders containing src/ subdir
SRC_MODULES := $(OTHER_MODULES) \
$(addprefix comp_EEE/,$(EEE_MODULES)) \
$(addprefix pack_DDD/,$(DDD_MODULES)) \
$(addprefix pack_AAA/,$(AAA_MODULES)) \
$(addprefix pack_CCC/, $(CCC_MODULES))
#All folders containing inc/ subdir
INCLUDE_MODULES := $(OTHER_MODULES) \
$(addprefix comp_EEE/,$(EEE_MODULES)) \
$(addprefix pack_DDD/,$(DDD_MODULES)) \
$(addprefix pack_AAA/,$(AAA_DIRS_INC)) \
$(addprefix pack_CCC/, $(CCC_MODULES))
#####################################
#WRAPPERS
ROOT_DIR_WRAPPERS := $(ROOT_DIR)../WRAPPERS/
LIST_WRAPPERS := WA WB WC WD
SRC_WRAPPERS := $(addprefix pack_Wrappers/csc_Wrapper,$(LIST_WRAPPERS))
#DRIVERS
LIST_DRIVERS := DA DB DC DD
DIR_DRIVERS := $(addprefix pack_Drivers/csc_Driver,$(LIST_DRIVERS))
SRC_DIRS_WRAPPERS := $(addsuffix /src,$(SRC_WRAPPERS))
INCLUDE_DIRS_WRAPPERS := $(addsuffix /inc,$(SRC_WRAPPERS)) \
$(addsuffix /inc,$(DIR_DRIVERS)) \
Common
#####################################
#LIB_1 INCLUDE
ROOT_DIR_LIB_1 := $(ROOT_DIR)../../ObjetsCompiles/LIB_1/
INCLUDE_DIRS_LIB_1 := dir1 dir2 dir3
#####################################
#LIB_2 INCLUDE
ROOT_DIR_LIB_2 := $(ROOT_DIR)../../ObjetsCompiles/LIB_2/include
INCLUDE_DIRS_LIB_2 := . dir1 dir2 dir3/subdir dir4
#####################################
#Add "." to find main.cpp
SRC_DIRS := $(addsuffix /src,$(SRC_MODULES)) .
INCLUDE_DIRS_SRC:= $(addsuffix /inc,$(INCLUDE_MODULES)) pack_ZZZ/comp_Without_Inc_Folder
#All include dirs, LIB_1 + LIB_2
INCLUDE_DIRS := $(addprefix -I$(ROOT_DIR),$(INCLUDE_DIRS_SRC)) \
$(addprefix -I$(ROOT_DIR_LIB_1),$(INCLUDE_DIRS_LIB_1)) \
$(addprefix -I$(ROOT_DIR_LIB_2),$(INCLUDE_DIRS_LIB_2))
INCLUDE_DIRS_CC := $(addprefix -I$(ROOT_DIR_WRAPPERS),$(INCLUDE_DIRS_WRAPPERS)) \
$(addprefix -I$(ROOT_DIR_LIB_2),$(INCLUDE_DIRS_LIB_2))
#All objects (all .cpp & all .c)
OBJS := $(foreach dir,$(SRC_DIRS), \
$(patsubst %.cpp,%.o,$(wildcard $(ROOT_DIR)$(dir)/*.cpp))) \
$(foreach dirs,$(SRC_DIRS_WRAPPERS), \
$(patsubst %.c,%.o,$(wildcard $(ROOT_DIR_WRAPPERS)$(dirs)/*.c)))
#All dependencies (same list as OBJS)
DEPS := $(foreach dir,$(SRC_DIRS), \
$(patsubst %.cpp,%.d,$(wildcard $(ROOT_DIR)$(dir)/*.cpp))) \
$(foreach dirs,$(SRC_DIRS_WRAPPERS), \
$(patsubst %.c,%.d,$(wildcard $(ROOT_DIR_WRAPPERS)$(dirs)/*.c)))
#Exclude files from build
#Win32 socket files + some misc
EXCLUDED_FILES_LIST := pack_AAA/comp_BBB/src/SocketWindowsOnLinuxForExample.cpp \
pack_BBB/comp_CCC/src/SomeOtherThingForWindows.cpp
EXCLUDED_FILES_PATH := $(addprefix $(ROOT_DIR),$(EXCLUDED_FILES_LIST))
#Remove some objects (compilation is done, but no link)
EXCLUDED_OBJS := $(patsubst %.cpp,%.o,$(EXCLUDED_FILES_PATH))
EXCLUDED_DEPS := $(patsubst %.cpp,%.d,$(EXCLUDED_FILES_PATH))
#Update OBJS & DEPS list with excluded files
OBJS := $(filter-out $(EXCLUDED_OBJS),$(OBJS))
DEPS := $(filter-out $(EXCLUDED_DEPS),$(DEPS))
#FLAGS for DEBUG and RELEASE compilation
CPPFLAGS := -D__CPPFLAG1__ -D__CPPFLAG2__
CFLAGS_D := -O0 -g2 -Wall -c -fmessage-length=0
CXXFLAGS_D := -O0 -g2 -Wall -c -fmessage-length=0 -m32 -mcpu=powerpc -Winline
CFLAGS_R := -O2 -g0 -Wall -c -fmessage-length=0
CXXFLAGS_R := -O2 -g0 -Wall -c -fmessage-length=0 -m32 -mcpu=powerpc -Winline
# L
LD_PATH := -L../../path_library_1 -L../../path_library_2
LD_LIBS := -lpthread_rt -lROHC -lpthread -lnative -lrtdm -lrt
MAP := $(PROG).map
# -s (to strip)
LD_FLAGS_D := -Wl,--wrap,pthread_create -Wl,--wrap,pthread_kill -Wl,-Map,$(MAP)
LD_FLAGS_R := -s -Wl,--wrap,pthread_create -Wl,--wrap,pthread_kill -Wl,-Map,$(MAP)
##################################################
#TARGETS
default: release
#Debug flags (-00 + -g2)
debug: CFLAGS := $(CFLAGS_D)
debug: CXXFLAGS := $(CXXFLAGS_D)
debug: LD_FLAGS := $(LD_FLAGS_D)
debug: all
#Release flags (-s + -02 + -g0)
release: CFLAGS := $(CFLAGS_R)
release: CXXFLAGS := $(CXXFLAGS_R)
release: LD_FLAGS := $(LD_FLAGS_R)
release: all
all: $(PROG)
# Tool invocations
$(PROG): $(OBJS)
#echo 'Building target: $#'
#$(CXX) $(LD_FLAGS) $(LD_PATH) -o "$(PROG)" $(OBJS) $(LD_LIBS)
#echo 'Finished building target: $#'
#echo ' '
# CXX compiler used by most of the code
%.o: %.cpp
#echo 'Building file: $<'
#$(CXX) $(CPPFLAGS) $(INCLUDE_DIRS) $(CXXFLAGS) -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
# CC compiler used by Wrappers only
%.o: %.c
#echo 'Building file: $<'
#$(CC) $(INCLUDE_DIRS_CC) $(CFLAGS) -MMD -MP -MF"$(#:%.o=%.d)" -MT"$(#:%.o=%.d)" -o "$#" "$<"
# Other Targets
clean:
-$(RM) $(OBJS) $(DEPS) $(PROG) $(MAP)
-#echo ' '
.PHONY: all clean dependents
.SECONDARY:
I am coding to the NRF51822 bluetooth chip, in Eclipse with GCC and a makefile that I maintain myself.
My problem is that every time I press build, it will compile everything, which is beginning to take quite some time. I am not that experienced in creating and maintaining make-files, so I have no idea where to start in order to get it to build incremtal instead?
My makefile is composed like this (I know there's a lot, and I haven't created this myself - found it in a tutorial, so I don't know what's relevant and what's not :-) ):
PROJECT_NAME := my_project
export OUTPUT_FILENAME
#MAKEFILE_NAME := $(CURDIR)/$(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))
MAKEFILE_NAME := $(MAKEFILE_LIST)
MAKEFILE_DIR := $(dir $(MAKEFILE_NAME) )
TEMPLATE_PATH = nrf51_sdk/toolchain/gcc
ifeq ($(OS),Windows_NT)
include $(TEMPLATE_PATH)/Makefile.windows
else
include $(TEMPLATE_PATH)/Makefile.posix
endif
MK := mkdir
RM := rm -rf
#echo suspend
ifeq ("$(VERBOSE)","1")
NO_ECHO :=
else
NO_ECHO := #
endif
# Toolchain commands
CC := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-gcc"
AS := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-as"
AR := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ar" -r
LD := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-ld"
NM := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-nm"
OBJDUMP := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objdump"
OBJCOPY := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-objcopy"
SIZE := "$(GNU_INSTALL_ROOT)/bin/$(GNU_PREFIX)-size"
#function for removing duplicates in a list
remduplicates = $(strip $(if $1,$(firstword $1) $(call remduplicates,$(filter-out $(firstword $1),$1))))
#source common to all targets
C_SOURCE_FILES += \
main.c \
file1.c \
file2.c \
file3.c \
file4.c \
#assembly files common to all targets
ASM_SOURCE_FILES = nrf51_sdk/toolchain/gcc/gcc_startup_nrf51.s
#includes common to all targets
INC_PATHS = -I Dir1/
INC_PATHS = -I Dir2
INC_PATHS += -I Dir3
INC_PATHS += -I Dir4
OBJECT_DIRECTORY = _build
LISTING_DIRECTORY =$(OBJECT_DIRECTORY)
OUTPUT_BINARY_DIRECTORY =$(OBJECT_DIRECTORY)
# Sorting removes duplicates
BUILD_DIRECTORIES := $(sort $(OBJECT_DIRECTORY) $(OUTPUT_BINARY_DIRECTORY) $(LISTING_DIRECTORY) )
#flags common to all targets
CFLAGS = -DSOFTDEVICE_PRESENT
CFLAGS += -DNRF51
CFLAGS += -DS110
CFLAGS += -DBOARD_PCA10028
CFLAGS += -DBLE_STACK_SUPPORT_REQD
CFLAGS += -mcpu=cortex-m0
CFLAGS += -mthumb -mabi=aapcs --std=gnu99
CFLAGS += -Wall -O0 -g3
CFLAGS += -mfloat-abi=soft
# keep every function in separate section. This will allow linker to dump unused functions
CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing
#CFLAGS += -flto -fno-builtin
# keep every function in separate section. This will allow linker to dump unused functions
LDFLAGS += -Xlinker -Map=$(LISTING_DIRECTORY)/$(OUTPUT_FILENAME).map
LDFLAGS += -mthumb -mabi=aapcs -L $(TEMPLATE_PATH) -T$(LINKER_SCRIPT)
LDFLAGS += -mcpu=cortex-m0
# let linker to dump unused sections
LDFLAGS += -Wl,--gc-sections
# use newlib in nano version
LDFLAGS += --specs=nano.specs -lc -lnosys
# Assembler flags
ASMFLAGS += -x assembler-with-cpp
ASMFLAGS += -DSOFTDEVICE_PRESENT
ASMFLAGS += -DNRF51
ASMFLAGS += -DS110
ASMFLAGS += -DBOARD_PCA10028
ASMFLAGS += -DBLE_STACK_SUPPORT_REQD
#default target - first one defined
default: clean nrf51422_xxac_s110
#building all targets
all: clean
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e cleanobj
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e nrf51422_xxac_s110
#target for printing all targets
help:
#echo following targets are available:
#echo nrf51422_xxac_s110
#echo flash_softdevice
C_SOURCE_FILE_NAMES = $(notdir $(C_SOURCE_FILES))
C_PATHS = $(call remduplicates, $(dir $(C_SOURCE_FILES) ) )
C_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILE_NAMES:.c=.o) )
ASM_SOURCE_FILE_NAMES = $(notdir $(ASM_SOURCE_FILES))
ASM_PATHS = $(call remduplicates, $(dir $(ASM_SOURCE_FILES) ))
ASM_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(ASM_SOURCE_FILE_NAMES:.s=.o) )
vpath %.c $(C_PATHS)
vpath %.s $(ASM_PATHS)
OBJECTS = $(C_OBJECTS) $(ASM_OBJECTS)
nrf51422_xxac_s110: OUTPUT_FILENAME := nrf51422_xxac_s110
nrf51422_xxac_s110: LINKER_SCRIPT=ble_app_hrs_gcc_nrf51.ld
nrf51422_xxac_s110: $(BUILD_DIRECTORIES) $(OBJECTS)
#echo Linking target: $(OUTPUT_FILENAME).out
$(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
$(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e finalize
## Create build directories
$(BUILD_DIRECTORIES):
echo $(MAKEFILE_NAME)
$(MK) $#
# Create objects from C SRC files
$(OBJECT_DIRECTORY)/%.o: %.c
#echo Compiling file: $(notdir $<)
#echo arm-none-eabi-gcc $(CFLAGS) $(INC_PATHS) -c -o $# $<
$(NO_ECHO)$(CC) $(CFLAGS) $(INC_PATHS) -c -o $# $<
# Assemble files
$(OBJECT_DIRECTORY)/%.o: %.s
#echo Compiling file: $(notdir $<)
$(NO_ECHO)$(CC) $(ASMFLAGS) $(INC_PATHS) -c -o $# $<
# Link
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out: $(BUILD_DIRECTORIES) $(OBJECTS)
#echo Linking target: $(OUTPUT_FILENAME).out
$(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
## Create binary .bin file from the .out file
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin: $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
#echo Preparing: $(OUTPUT_FILENAME).bin
$(NO_ECHO)$(OBJCOPY) -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin
## Create binary .hex file from the .out file
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex: $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
#echo Preparing: $(OUTPUT_FILENAME).hex
$(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex
finalize: genbin genhex echosize
genbin:
#echo Preparing: $(OUTPUT_FILENAME).bin
$(NO_ECHO)$(OBJCOPY) -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).bin
## Create binary .hex file from the .out file
genhex:
#echo Preparing: $(OUTPUT_FILENAME).hex
$(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex
echosize:
-#echo ""
$(NO_ECHO)$(SIZE) $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
-#echo ""
clean:
$(RM) $(BUILD_DIRECTORIES)
cleanobj:
$(RM) $(BUILD_DIRECTORIES)/*.o
flash: $(MAKECMDGOALS)
#echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$<.hex
nrfjprog --reset --program $(OUTPUT_BINARY_DIRECTORY)/$<.hex)
## Flash softdevice
flash_softdevice:
#echo Flashing: s110_softdevice.hex
nrfjprog --reset --program nrf51_sdk/softdevice/s110/hex/s110_softdevice.hex
all: clean
check this line. The default (first) Target of your Makefile depends on clean, so before any build is started, the clean target is executed that likely will remove all built files, to rebuild them.
Drop the clean and you should get the incremental behaviour make was designed for.
hen I do make clean it complains about missing files. In particular it complains about mapnameserver.hthat is included in nstest.cc and nstime.cc.
I thought that doing make clean would ignore all other targets, even implicit ones.
What I want is to be able to do make clean and make vectornameserver without make complaining about the headers that nstest.cc and nstime.cc includes that I have not yet written. Is this possible?
Below is the files in the src dir
nameserverinterface.h
nstest.cc
nstime.cc
vectornameserver.cc
vectornameserver.h
And this is the Makefile
#
# Makefile for CPP
#
# Compiler and compiler options:
CC = /usr/local/bin/clang++
CXX = /usr/local/bin/clang++
CXXFLAGS = -c -pipe -O2 -Wall -W -ansi -pedantic-errors
CXXFLAGS += -Wmissing-braces -Wparentheses -Wold-style-cast
CXXFLAGS += -std=c++11 -stdlib=libc++ -nostdinc++
CXXFLAGS += -I/Users/einar/devel/libcxx/include/
LDFLAGS = -stdlib=libc++
LDLIBS = -L/Users/einar/devel/libcxx/lib/
SRCDIR = ../src
LIBDIR = ../lib
BINDIR = ../bin
DEPDIR = ../dep
VPATH = $(SRCDIR):$(LIBDIR):$(BINDIR):$(DEPDIR)
LIB_INSTALL =
BIN_INSTALL =
SRC = $(wildcard $(SRCDIR)/*.cc)
OBJ = $(notdir $(SRC:.cc=.o))
DEP = $(addprefix $(DEPDIR)/, $(notdir $(SRC:.cc=.d)))
PROGS = vectornameserver
MAKEDEPEND = $(CXX) -MM $(CPPFLAGS) -o $*.d $<
CP = /bin/cp
###
#
# Phony targets
#
###
.PHONY: all
all: $(PROGS)
.PHONY: folder_setup
folder_setup:
mkdir -p $(SRCDIR)
mkdir -p $(LIBDIR)
mkdir -p $(BINDIR)
mkdir -p $(DEPDIR)
.PHONY: clean
clean:
#$(RM) $(OBJ)
.PHONY: cleaner
cleaner:
#$(RM) $(OBJ)
#$(RM) $(PROGS)
#$(RM) $(DEP)
#$(RM) $(wildcard $(DEPDIR)/*.d*)
###
#
# Set up targets for program files in this section
# a rule should look like:
# program: obj1.o obj2.o ...
#
###
vectornameserver : vectornameserver.o
###
#
# In this section automatic dependencies are handled.
#
###
$(addprefix $(DEPDIR)/, %.d): %.cc
#set -e; rm -f $#; \
$(CXX) -MM $(CPPFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $#: ,g' < $#.$$$$ \
> $#; rm -f $#.$$$$
###
#
# Include the automatically generated dependency files
#
###
include $(DEP)
Thanks in advance.
The problem is that you have an include directive in the makefile. This implicitly makes all the included dependency files implicit targets that must be refreshed BEFORE the primary target can be run. It is those rules that are running the compiler and giving you the errors.
Since generally you don't want/need the dependency files if you're just doing a make clean, the usual thing is to wrap appropriate ifs around the include:
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(MAKECMDGOALS),cleaner)
-include $(DEP)
endif
endif
This will avoid trying to include the depfiles (and thus regenerate them) if you do make clean or make cleaner. In addition, the - prefix on the include supresses warnings about the depfiles not existing when you first run make (it will (re)generate them and reread the makefile and depfiles if need be.)